Antenna Violation Avoidance/Fixing for X-clock routing

Abstract

As the IC fabrication technology gets into the nanometer era, antenna effect plays an important role in determining the yield and reliability of VLSI circuits. This work proposes a discharge-path-based antenna effect detection method. Based on the proposed detection method, two novel jumper insertion and layer assignment algorithms are presented for fixing antenna violations. Additionally, via delay is considered in delay calculation, and wire sizing technique is applied for clock skew compensation. Given an X-architecture clock tree with n clock sinks, layer configuration, and the upper bound for antenna effect, the proposed PADJILA algorithm runs in O(n2) to achieve antenna violation free. Experimental results on benchmarks show that our work significantly outperforms than the existing works.