Chenyue Ma, Hao Wang, Xiufang Zhang, F. He, Yadong He, Xing Zhang, Xinnan Lin
{"title":"Asymmetric issues of FinFET device after hot carrier injection and impact on digital and analog circuits","authors":"Chenyue Ma, Hao Wang, Xiufang Zhang, F. He, Yadong He, Xing Zhang, Xinnan Lin","doi":"10.1109/ISQED.2010.5450542","DOIUrl":null,"url":null,"abstract":"This paper presents the asymmetric issue of FinFET device after hot carrier injection (HCI) effect and impact on the digital and analog circuits. The interface state distribution along the FinFET channel is first extracted from hot carrier injection experimental data, and then develops a compact FinFET model to simulate the impact on asymmetric distribution of interface states to the device characteristics. The results show that the asymmetric degradation is much more significant in Ids-Vds characteristics than in Ids-Vgs characteristics. On the other hand, digital and analogy circuits exhibit different asymmetric performance degradation in various operation cases.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 11th International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2010.5450542","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents the asymmetric issue of FinFET device after hot carrier injection (HCI) effect and impact on the digital and analog circuits. The interface state distribution along the FinFET channel is first extracted from hot carrier injection experimental data, and then develops a compact FinFET model to simulate the impact on asymmetric distribution of interface states to the device characteristics. The results show that the asymmetric degradation is much more significant in Ids-Vds characteristics than in Ids-Vgs characteristics. On the other hand, digital and analogy circuits exhibit different asymmetric performance degradation in various operation cases.