Low power clock gates optimization for clock tree distribution

Abstract

Clock gating technique had become one of the major dynamic power saving approaches in today low power digital circuit design. In this paper, we present a new physical clock gates optimization technique using splitting and merging algorithm that works on both single level and multiple levels clock gating design. The algorithm is built on top of the standard EDA flow by running two passes clock tree synthesis. The first pass is to obtain the clock buffer location for clock gate swapping and the second pass will build the clock tree based on the optimum clock gate location. The merging algorithm will then be used to improve the overall clock tree power. The results on the industrial design show the improvement on overall clock tree power using aforementioned algorithm.