GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996最新文献

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Wide bandgap semiconductor electronic devices for high frequency applications 用于高频应用的宽带隙半导体电子器件
R. Trew, M. Shin, V. Gatto
{"title":"Wide bandgap semiconductor electronic devices for high frequency applications","authors":"R. Trew, M. Shin, V. Gatto","doi":"10.1109/GAAS.1996.567625","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567625","url":null,"abstract":"The microwave performance of electronic devices fabricated from SiC and GaN is described. The investigation makes use of theoretical simulations and the results are compared to experimental measurements. Excellent agreement between the simulated and measured data is obtained. It is demonstrated that microwave power amplifiers fabricated from SiC and GaN based semiconductors offer superior RF power performance, particularly at elevated temperature compared to comparable components fabricated from GaAs MESFET's. In particular, room temperature RF output power on the order of 4 W/mm with power-added efficiency approaching the ideal values for class A and B operation is available. These devices are likely to find application in power amplifiers for base station transmitters for cellular telephone systems, power modules for phased-array radars, and other applications. The devices are particularly attractive for applications that require operation at elevated temperature.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129354426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
GaAs ICs in commercial OC-192 equipment 商用OC-192设备中的GaAs集成电路
H. Willemsen, D. Nicholson
{"title":"GaAs ICs in commercial OC-192 equipment","authors":"H. Willemsen, D. Nicholson","doi":"10.1109/GAAS.1996.567626","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567626","url":null,"abstract":"OC-192, with a data rate of 9.953 Gb/s, is the fastest commercial fiber-optic transport system available today. As with lower bit-rate equipment, III-V compound semiconductors play a large role in OC-192. This paper describes the technology selection, circuit design and high-speed packaging needed for the successful introduction of OC-192.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131358700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
80 GHz AlGaAs HBT oscillator
I. Aoki, K. Tezuka, H. Matsuura, S. Kobayashi, T. Fujita, A. Miura
{"title":"80 GHz AlGaAs HBT oscillator","authors":"I. Aoki, K. Tezuka, H. Matsuura, S. Kobayashi, T. Fujita, A. Miura","doi":"10.1109/GAAS.1996.567887","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567887","url":null,"abstract":"This paper describes an 80 GHz monolithic fundamental frequency oscillator using an AlGaAs heterojunction bipolar transistor technology. The transistor performs a unity current gain frequency f/sub T/=130 GHz and a maximum frequency of oscillation f/sub max/=180 GHz. The output signal level of the oscillator is -9 dBm, and the SSB phase noise is estimated as -80 dBc/Hz at 1 MHz offset frequency. A couple of coplanar waveguides are utilized for resonators.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132192280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A 560 mW, 21% power-added efficiency V-band MMIC power amplifier 560mw, 21%功率增益效率v波段MMIC功率放大器
O. Tang, K. Duh, S. Liu, P.M. Smith, W. Kopp, T. Rogers, D. Pritchard
{"title":"A 560 mW, 21% power-added efficiency V-band MMIC power amplifier","authors":"O. Tang, K. Duh, S. Liu, P.M. Smith, W. Kopp, T. Rogers, D. Pritchard","doi":"10.1109/GAAS.1996.567819","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567819","url":null,"abstract":"In this paper we report the development of two V-band MMIC power amplifiers, based on 0.1 mm pseudomorphic HEMT (PHEMT) technology, that significantly advance the state of the art of V-band power MMIC performance. The first, a single-ended design, measures on-wafer 293 mW output power with a record 26% PAE and 9.9 dB power gain at 62.5 GHz. The second MMIC is a balanced design with on-chip input and output Lange Couplers. It delivers a record 564 mW output power (27.5 dBm) with 21% PAE and 9.8 dB power gain. This represents more than a 50% increase in output power, together with record PAE and power gain. The MMICs have been designed for high reliability satellite communications, with full passivation, excellent thermal properties, backed-off drain bias, and have been fabricated on 3-inch wafers. These excellent first pass MMIC results can be attributed to the use of an optimized 0.1 mm PHEMT cell structure, a design based on on-wafer RF measurements and a new and very accurate large signal analytical PHEMT model.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134109450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Improved reliability self-aligned C/X-band monolithic power HBT amplifiers fabricated with a low-stress process 采用低应力工艺制备的可靠性提高的自对准C/ x波段单片功率HBT放大器
T. Henderson, T.S. Kim
{"title":"Improved reliability self-aligned C/X-band monolithic power HBT amplifiers fabricated with a low-stress process","authors":"T. Henderson, T.S. Kim","doi":"10.1109/GAAS.1996.567629","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567629","url":null,"abstract":"We report extensive reliability testing and analysis on GaAs single-finger C/X-band HBTs fabricated for monolithic amplifiers with a low-stress process, The HBTs are self-aligned to maximize RF power performance, with ledge passivation and a low stress epitaxial base and dielectric overcoat to improve reliability. Performed from T/sub jo/=185-340/spl deg/C and J/sub co/=25-50 kA/cm/sup 2/. The temperature and current dependence of the various observed failure modes and mechanisms are described. Long-term (>3000 hour), low temperature (<250/spl deg/C), high current stress tests are found to be accurate indicators of how HBTs degrade under nominal operating conditions. Shorter, high temperature tests may lead to excessively optimistic predictions of activation energy and median time to failure.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133554824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Off-state breakdown walkout in high-power PHEMT's 大功率PHEMT的非正常故障罢工
Y. Chou, G. Li, K. Yu, C. Wu, P. Chu, L. Hou, T. Midford
{"title":"Off-state breakdown walkout in high-power PHEMT's","authors":"Y. Chou, G. Li, K. Yu, C. Wu, P. Chu, L. Hou, T. Midford","doi":"10.1109/GAAS.1996.567633","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567633","url":null,"abstract":"PECVD nitride passivated high-power AlGaAs/InGaAs PHEMTs processed with different surface conditions and on epitaxial wafers from different vendors were fabricated to study the off-state breakdown walkout. It has been shown that breakdown walkout of passivated high-power PHEMTs depends on the surface process conditions and to a less degree on the starting wafers. The breakdown walkout shows no noticeable recovery after annealing at 240/spl deg/C for 400 hours, indicating a permanent improvement. The results suggest an alternative to optimize the PHEMT's process for reliability and to improve the breakdown voltage.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132623804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 500 MHz complementary gallium arsenide clock multiplier 一个500兆赫互补砷化镓时钟倍增器
V. Mazzotta, D. Foster
{"title":"A 500 MHz complementary gallium arsenide clock multiplier","authors":"V. Mazzotta, D. Foster","doi":"10.1109/GAAS.1996.567899","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567899","url":null,"abstract":"This paper reports a 500 MHz complementary gallium-arsenide (CGaAs/sup TM/) clock multiplier. The design was implemented in Motorola's 0.7 /spl mu/m complementary gallium-arsenide (CGaAs/sup TM/) process. The goal was to demonstrate operation of an on-chip CGaAs/sup TM/ clock multiplier based on a phase-locked loop at low voltage. This design is similar to implementations that have been fabricated with silicon CMOS. However, CMOS implementations require feature sizes of 0.4 /spl mu/m to achieve the same performance as 0.7 /spl mu/m CGaAs/sup TM/. The design demonstrates the flexibility of this process to tune different sections of the circuitry to provide either high performance where necessary with greater than 500 MHz speeds using p-load DCFL designs, or much lower dynamic power consumption using complementary CMOS like designs. This paper discusses the design and implementation of the clock multiplier. Test results are presented. The design measures 1.21 mm/sup 2/, including the fully integrated passive filter. The clock multiplier can lock to and multiply reference signals between frequencies 3.2 MHz and 7.7 MHz. The power dissipation is 15 mW at an input frequency of 5 MHz and a power supply voltage of 1.2 V.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114451734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Slip defect generation on GaAs wafers during high temperature process: a thermoelastic study from a crystallographic viewpoint 高温过程中砷化镓晶片滑移缺陷的产生:从晶体学角度的热弹性研究
S. Sawada, H. Yoshida, M. Kiyama, H. Mukai, R. Nakai, T. Takebe, M. Tatsumi, M. Kaji, K. Fujita
{"title":"Slip defect generation on GaAs wafers during high temperature process: a thermoelastic study from a crystallographic viewpoint","authors":"S. Sawada, H. Yoshida, M. Kiyama, H. Mukai, R. Nakai, T. Takebe, M. Tatsumi, M. Kaji, K. Fujita","doi":"10.1109/GAAS.1996.567635","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567635","url":null,"abstract":"In this work we investigate the mechanism of slip defect generation, using a simple heat flow simulation during an MBE process, a wafer heating apparatus, and a thermoelastic analysis from a crystallographic viewpoint. We find that the slip defect pattern predicted from the analysis agrees with the experiment and confirm that slip defects are prone to occur at orientation flat (OF) and notch edge.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124888862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A low-power enable/disable GaAs MESFET differential logic 低功耗启用/禁用GaAs MESFET差分逻辑
R. Ribas, A. Bernal, A. Guyot
{"title":"A low-power enable/disable GaAs MESFET differential logic","authors":"R. Ribas, A. Bernal, A. Guyot","doi":"10.1109/GAAS.1996.567742","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567742","url":null,"abstract":"In this work, a novel and straightforward enable/disable GaAs MESFET Differential Logic (EMDL) structure is presented. EMDL is compatible with DCFL and some reported MESFET differential logic families, like DPTL, DCVS and DC/sup 2/FL. No power dissipation during the standby state, fewer transistors per logic function and noise immunity are its more interesting features. The EMDL can be efficiently applied in both synchronous and asynchronous designs. EMDL iterative network micropipeline applications are detailed. An 8-bit ripple carry adder was successfully fabricated and tested verifying the EMDL functionality and performance characteristics.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131441597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A complementary GaAs PLL clock multiplier with wide-bandwidth and low-voltage operation 具有宽带宽和低电压工作的互补GaAs锁相环时钟乘法器
Sean Stetson, Richard B. Brown
{"title":"A complementary GaAs PLL clock multiplier with wide-bandwidth and low-voltage operation","authors":"Sean Stetson, Richard B. Brown","doi":"10.1109/GAAS.1996.567898","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567898","url":null,"abstract":"This paper reports a phase-locked loop clock multiplier designed for wide-bandwidth operation at supply voltages of 0.9 V to 1.5 V. Implemented in Motorola's complementary GaAs (CGaAs/sup TM/) process, the target application is the PUMA processor, a multi-chip microprocessor based on the PowerPC instruction set architecture. This system operates on an input system clock of 100-125 MHz, while the processor clock is targeted to run at a frequency of 1 GHz. Phase-locked loop clock multiplication factors of 2 to 16 are supported, while the achievable output frequency ranges from 110 MHz to 775 MHz. The chip utilizes Motorola's 0.7 /spl mu/m CGaAs/sup TM/ process and is entirely implemented with the direct-coupled FET standard cell library developed for the PUMA project. This paper discusses the design and implementation of the clock multiplier. Test results are presented. The design measures 1.4 mm/sub 2/, including the fully integrated passive filter. The core power dissipation is 300 mW at 1.5 V, and 36 mW at 0.9 V.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127492272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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