A low-power enable/disable GaAs MESFET differential logic

R. Ribas, A. Bernal, A. Guyot
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引用次数: 2

Abstract

In this work, a novel and straightforward enable/disable GaAs MESFET Differential Logic (EMDL) structure is presented. EMDL is compatible with DCFL and some reported MESFET differential logic families, like DPTL, DCVS and DC/sup 2/FL. No power dissipation during the standby state, fewer transistors per logic function and noise immunity are its more interesting features. The EMDL can be efficiently applied in both synchronous and asynchronous designs. EMDL iterative network micropipeline applications are detailed. An 8-bit ripple carry adder was successfully fabricated and tested verifying the EMDL functionality and performance characteristics.
低功耗启用/禁用GaAs MESFET差分逻辑
在这项工作中,提出了一种新颖而直接的使能/禁用GaAs MESFET差分逻辑(EMDL)结构。EMDL兼容DCFL和一些已报道的MESFET差分逻辑家族,如DPTL、DCVS和DC/sup 2/FL。待机状态无功耗、每个逻辑函数的晶体管数更少以及抗噪声是其更有趣的特点。EMDL可以有效地应用于同步和异步设计。详细介绍了EMDL迭代网络微管道的应用。成功制作了一个8位纹波进位加法器,并对其进行了测试,验证了EMDL的功能和性能特征。
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