A complementary GaAs PLL clock multiplier with wide-bandwidth and low-voltage operation

Sean Stetson, Richard B. Brown
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引用次数: 0

Abstract

This paper reports a phase-locked loop clock multiplier designed for wide-bandwidth operation at supply voltages of 0.9 V to 1.5 V. Implemented in Motorola's complementary GaAs (CGaAs/sup TM/) process, the target application is the PUMA processor, a multi-chip microprocessor based on the PowerPC instruction set architecture. This system operates on an input system clock of 100-125 MHz, while the processor clock is targeted to run at a frequency of 1 GHz. Phase-locked loop clock multiplication factors of 2 to 16 are supported, while the achievable output frequency ranges from 110 MHz to 775 MHz. The chip utilizes Motorola's 0.7 /spl mu/m CGaAs/sup TM/ process and is entirely implemented with the direct-coupled FET standard cell library developed for the PUMA project. This paper discusses the design and implementation of the clock multiplier. Test results are presented. The design measures 1.4 mm/sub 2/, including the fully integrated passive filter. The core power dissipation is 300 mW at 1.5 V, and 36 mW at 0.9 V.
具有宽带宽和低电压工作的互补GaAs锁相环时钟乘法器
本文报道了一种锁相环时钟乘法器,设计用于在0.9 V至1.5 V电源电压下的宽带工作。在摩托罗拉的互补GaAs (CGaAs/sup TM/)工艺中实现,目标应用是PUMA处理器,一种基于PowerPC指令集架构的多芯片微处理器。该系统运行在100-125 MHz的输入系统时钟上,而处理器时钟的目标运行频率为1 GHz。锁相环时钟倍增倍数为2 ~ 16,可实现输出频率范围为110 MHz ~ 775 MHz。该芯片采用摩托罗拉的0.7 /spl mu/m CGaAs/sup TM/工艺,完全采用为PUMA项目开发的直接耦合场效应管标准单元库实现。本文讨论了时钟乘法器的设计与实现。给出了试验结果。该设计尺寸为1.4 mm/sub 2/,包括完全集成的无源滤波器。在1.5 V时,核心功耗为300mw,在0.9 V时,核心功耗为36mw。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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