发布求助
文献互助 智能选刊 最新文献

2016 IEEE East-West Design & Test Symposium (EWDTS)最新文献

筛选
英文 中文
Using high-level synthesis for rapid design of video processing pipes 采用高级合成技术进行视频处理管道的快速设计
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807644
A. E. Guzel, Vecdi Emre Levent, M. Tosun, M. A. Ozkan, Toygar Akgun, Duygu Buyukaydin, Cengiz Erbas, H. F. Ugurdag
{"title":"Using high-level synthesis for rapid design of video processing pipes","authors":"A. E. Guzel, Vecdi Emre Levent, M. Tosun, M. A. Ozkan, Toygar Akgun, Duygu Buyukaydin, Cengiz Erbas, H. F. Ugurdag","doi":"10.1109/EWDTS.2016.7807644","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807644","url":null,"abstract":"In this work, we share our experience in using High-Level Synthesis (HLS) for rapid development of an optical flow design on FPGA. We have performed HLS using Vivado HLS as well as a HLS tool we have developed for the optical flow design at hand and similar video processing problems. The paper first describes the design problem we have and then discusses our own HLS tool. The tool we developed has turned out to be pretty general-purpose except for the ability to handle cyclic inter-iteration dependencies. It also introduces some novel concepts to HLS, such as “pipelined multiplexers”. The synthesis results show that we can achieve better timing or better area results compared to Vivado HLS. Furthermore, the Verilog RTL our HLS tool outputs is much more readable than the one from Vivado HLS. This makes it much easier for the designer to debug and modify the RTL.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125895011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The modeling of characteristics of the patch antenna with non-uniform substrate metamaterial 非均匀基板超材料贴片天线特性的建模
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807718
N. N. Kisel, V. A. Cheremisov, Dmitry S. Derachitc
{"title":"The modeling of characteristics of the patch antenna with non-uniform substrate metamaterial","authors":"N. N. Kisel, V. A. Cheremisov, Dmitry S. Derachitc","doi":"10.1109/EWDTS.2016.7807718","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807718","url":null,"abstract":"Analysis of the effectiveness of metamaterials as a substrate of microstrip antennas for the purpose of providing broadband antenna while reducing the size and increasing the antenna gain are carried out in the report. As an example of the calculation of a microstrip antenna characteristics are given in which the substrate is a metamaterial unit cell in the form of nested open rings (SRR - split ring resonator). The resonant frequency of the resonator is determined by the length of the open rings, the size of the gap and the thickness of the rings. the basic laws of influence on the characteristics of microstrip antennas geometrical sizes of rings are obtained, the calculation results are summarized in the form of nomograms. The case of the planar antenna and conformal microstrip antenna located on a cylindrical surface is considered. Research are conducted by a specialized package FEKO.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125441273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
NBTI mitigation by M-IVC with input duty cycle and randomness constraints 具有输入占空比和随机约束的M-IVC抑制NBTI
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807666
Maoxiang Yi, Xiaohong Liu, Qingwu Wu, Tianming Ni, Zhengfeng Huang, Huaguo Liang
{"title":"NBTI mitigation by M-IVC with input duty cycle and randomness constraints","authors":"Maoxiang Yi, Xiaohong Liu, Qingwu Wu, Tianming Ni, Zhengfeng Huang, Huaguo Liang","doi":"10.1109/EWDTS.2016.7807666","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807666","url":null,"abstract":"An improved M-IVC scheme is proposed to mitigate the NBTI aging of circuit in standby mode, in which the input control vectors are randomly generated under constraint of the input duty cycles obtained by genetic algorithm. The experimental results show that compared with the existing M-IVC method, the circuit time delay degradation can be improved by 51.5% on average when S/A is 5/5 and the effectiveness gets better as S/A increases.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133487895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Monitoring system of vibration impacts on the structure of overhead catenary of high-speed railway lines 高速铁路架空接触网结构振动冲击监测系统
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807691
D. Efanov, G. Osadchy, D. Sedykh, Dmitry Pristensky, Dmitry Barch
{"title":"Monitoring system of vibration impacts on the structure of overhead catenary of high-speed railway lines","authors":"D. Efanov, G. Osadchy, D. Sedykh, Dmitry Pristensky, Dmitry Barch","doi":"10.1109/EWDTS.2016.7807691","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807691","url":null,"abstract":"The results of technical solutions proposed by the authors for application during continuous monitoring of vibration impacts in the overhead catenary cables and wires on the high-speed railway line “St. Petersburg - Moscow” (Russian Federation) are described herein. Specialized design of sensor to be attached at the control points on the overhead catenary cables and wires, including the accelerometer of MEMS type and built-in controller is fulfilled. The monitoring results are being processed by the integrated controller directly on the diagnostics site and transmitted via a radio-frequency channel with a specially designated frequency to the data hubs of the line service stations. The results of experiments for vibration-based diagnostics of the overhead catenary on the test site as well as some results of practical application are presented and highlighted in our article. The classification of events, being recorded via the designed diagnostic tool is completed, as well as the ways of improving continuous monitoring system of the railway overhead catenary are outlined based on the results of trial operation.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131570412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Cloud service for university E-government 大学电子政务云服务
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807660
O. Mishchenko, V. Abdullayev, E. Litvinova, V. Hahanov, S. Chumachenko, Anastasya Hahanova
{"title":"Cloud service for university E-government","authors":"O. Mishchenko, V. Abdullayev, E. Litvinova, V. Hahanov, S. Chumachenko, Anastasya Hahanova","doi":"10.1109/EWDTS.2016.7807660","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807660","url":null,"abstract":"Cyber culture of the smart university creates the social significance of technological leadership. Internet and cyberspace change all the processes of life of each person. It is necessary to create a new market-oriented model of scientific and educational processes within the Smart Cyber University (SCU). The concept integrates the achievements of classical universities, technological cyber culture, and human desire for perfection through continuous education throughout their lives. The basis of the SCU is the structural organization of cyber physical system, focused on cloud management of the scientific and educational processes through its precise digital monitoring. The structure of the classical university includes the following components, which have to be digitized: science, education, human resources, infrastructure, relationships, management, roadmap, resources, and products. Legitimate relations are the main part of the SCU, which are based on the metric for measuring the quality of all the processes and phenomena. This makes it possible to completely eliminate corruption in the processes of resource distribution and personnel management through the metric evaluation of the activities of university departments and employees. SCU cloud services are focused on developing countries in order to help the progressive university leaders to eliminate the corruption, implement paperless technology for monitoring and management of scientific and educational processes, significantly reduce the time costs for organizing educational and scientific processes through online-cooperation. Cloud mobile management of SCU based on the metric measurement of all processes allows attracting foreign investment in scientific research, improve the quality of educational services and scientific results, the performance of the creative work of scientists and their standard of living.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134096956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Critical path selection under NBTI/PBTI aging for adaptive frequency tuning 基于NBTI/PBTI老化的自适应调谐关键路径选择
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807652
Andres F. Gomez, V. Champac
{"title":"Critical path selection under NBTI/PBTI aging for adaptive frequency tuning","authors":"Andres F. Gomez, V. Champac","doi":"10.1109/EWDTS.2016.7807652","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807652","url":null,"abstract":"Critical Paths Monitoring is an efficient technique to overcome transistor aging. A methodology to select critical paths to be monitored at design phase is proposed. A spatial correlation approach is used to perform Statistical Timing Analysis at design phase. Critical paths are selected for various aging workload profiles to avoid worst-case assumptions. The results show that up to 16x less paths are selected compared to path selection using worst-case aging. Moreover, the selected paths match well with those selected using spatial correlation extracted from final circuit layout.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"6 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Synthesis of combinational circuits from the truth tables in “Kovcheg” CAD design flow 基于“Kovcheg”CAD设计流程真值表的组合电路合成
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807708
V. Aleshina, S. Frolov, M. Makarceva, A. Golenkevich
{"title":"Synthesis of combinational circuits from the truth tables in “Kovcheg” CAD design flow","authors":"V. Aleshina, S. Frolov, M. Makarceva, A. Golenkevich","doi":"10.1109/EWDTS.2016.7807708","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807708","url":null,"abstract":"This paper describes the system implemented in “Kovcheg” CAD for integrated circuit design automation. This system allows the user to specify combinational circuits in the form of truth tables. Truth table input values can be specified in automatic mode with a full range of input combinations or in manual mode for specific sets only. The mapping process to the gate array cell library with parameterized constraints as well as the automatic circuit representation of the schematic view in the graphic editor are also described.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131606326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel technique to detect Aging in analog/mixed-signal circuits 一种新的模拟/混合信号电路老化检测技术
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807643
Mehrnaz Ahmadi, Rasoul Jafari
{"title":"A novel technique to detect Aging in analog/mixed-signal circuits","authors":"Mehrnaz Ahmadi, Rasoul Jafari","doi":"10.1109/EWDTS.2016.7807643","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807643","url":null,"abstract":"The increasing complexity of current and future ICs has the issue of more complex and more expensive test especially in mixed signal circuit designs. As Opamps are used in a wide applications of analog/mixed-signal circuits, this paper presents a BIST technique to detect aging in mixed signal circuits. This technique uses the internal Opamps as their aging sensors. The basic idea of our proposed technique relies on detecting changes on slew rate of Opamps inside mixed-signal circuits. Our Hspice simulations show that our proposed architecture is able to fully detect aging in our test circuit.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122754888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ILP based don't care bits filling technique for reducing capture power 基于ILP的任意位填充技术，降低捕获功率
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807649
Rohini Gulve, Virendra Singh
{"title":"ILP based don't care bits filling technique for reducing capture power","authors":"Rohini Gulve, Virendra Singh","doi":"10.1109/EWDTS.2016.7807649","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807649","url":null,"abstract":"Modern design for testability (DFT) techniques support the application of non-functional vectors with increased controllability, observability and ease of test generation complexity. High power demand due to excessive switching activity in test mode causes false failure, test escape and reliability issues. Therefore, generating power safe pattern test is an active research topic. Don't care bits present in the test set can be filled to minimize the capture power consumption due to delay test. In this paper, we formulate an optimization problem using integer linear programing. The proposed ILP based methodology is applicable for both launch-on-capture (LOC) and lunch-of-shift (LOS) schemes under minimization constraints for total capture switching activity reduction without any alteration in already existing automatic test pattern generation (ATPG) tools. Proposed formulation reduces peak weighted switching activity by 25% to 60% and average by 40% to 88% w.r.t randomly filled patterns.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122558310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Dynamic FPGA-accelerator sharing among concurrently running virtual machines 并发运行的虚拟机之间的动态fpga加速器共享
2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI: 10.1109/EWDTS.2016.7807639
Hamid Nasiri, M. Goudarzi
{"title":"Dynamic FPGA-accelerator sharing among concurrently running virtual machines","authors":"Hamid Nasiri, M. Goudarzi","doi":"10.1109/EWDTS.2016.7807639","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807639","url":null,"abstract":"Using an FPGA as a hardware accelerator has been prevalent, to speed up compute intensive workloads. However, employing an accelerator in virtualized environment enhances complexity, because accessing the accelerator from virtual machines has significant overhead and sharing it needs some considerations. We have implemented adequate infrastructure to share an FPGA-based accelerator between multiple virtual machines with negligible access overhead which dynamically implements virtual machines' accelerators. In our architecture each user process from a virtual machine can directly access the FPGA over PCIe link and reconfigure its accelerator in the specified part of FPGA at run-time. The results of executing two different applications in two separated virtual machines using our shared accelerator show reducing the execution time of both applications and increasing performance of the entire system in practice. In this evaluation the overall speedup of our method was 6.3x while the best speedup of dedicated accelerator scenarios was 3.4x.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121974415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信