{"title":"基于NBTI/PBTI老化的自适应调谐关键路径选择","authors":"Andres F. Gomez, V. Champac","doi":"10.1109/EWDTS.2016.7807652","DOIUrl":null,"url":null,"abstract":"Critical Paths Monitoring is an efficient technique to overcome transistor aging. A methodology to select critical paths to be monitored at design phase is proposed. A spatial correlation approach is used to perform Statistical Timing Analysis at design phase. Critical paths are selected for various aging workload profiles to avoid worst-case assumptions. The results show that up to 16x less paths are selected compared to path selection using worst-case aging. Moreover, the selected paths match well with those selected using spatial correlation extracted from final circuit layout.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"6 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Critical path selection under NBTI/PBTI aging for adaptive frequency tuning\",\"authors\":\"Andres F. Gomez, V. Champac\",\"doi\":\"10.1109/EWDTS.2016.7807652\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Critical Paths Monitoring is an efficient technique to overcome transistor aging. A methodology to select critical paths to be monitored at design phase is proposed. A spatial correlation approach is used to perform Statistical Timing Analysis at design phase. Critical paths are selected for various aging workload profiles to avoid worst-case assumptions. The results show that up to 16x less paths are selected compared to path selection using worst-case aging. Moreover, the selected paths match well with those selected using spatial correlation extracted from final circuit layout.\",\"PeriodicalId\":364686,\"journal\":{\"name\":\"2016 IEEE East-West Design & Test Symposium (EWDTS)\",\"volume\":\"6 4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE East-West Design & Test Symposium (EWDTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EWDTS.2016.7807652\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2016.7807652","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Critical path selection under NBTI/PBTI aging for adaptive frequency tuning
Critical Paths Monitoring is an efficient technique to overcome transistor aging. A methodology to select critical paths to be monitored at design phase is proposed. A spatial correlation approach is used to perform Statistical Timing Analysis at design phase. Critical paths are selected for various aging workload profiles to avoid worst-case assumptions. The results show that up to 16x less paths are selected compared to path selection using worst-case aging. Moreover, the selected paths match well with those selected using spatial correlation extracted from final circuit layout.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
