Critical path selection under NBTI/PBTI aging for adaptive frequency tuning

Abstract

Critical Paths Monitoring is an efficient technique to overcome transistor aging. A methodology to select critical paths to be monitored at design phase is proposed. A spatial correlation approach is used to perform Statistical Timing Analysis at design phase. Critical paths are selected for various aging workload profiles to avoid worst-case assumptions. The results show that up to 16x less paths are selected compared to path selection using worst-case aging. Moreover, the selected paths match well with those selected using spatial correlation extracted from final circuit layout.