基于“Kovcheg”CAD设计流程真值表的组合电路合成

2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI:10.1109/EWDTS.2016.7807708

V. Aleshina, S. Frolov, M. Makarceva, A. Golenkevich

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引用次数: 0

摘要

本文介绍了在“Kovcheg”集成电路设计自动化CAD中实现的系统。该系统允许用户以真值表的形式指定组合电路。真值表输入值可以在具有全范围输入组合的自动模式下指定，或者仅在特定集合的手动模式下指定。本文还描述了带参数化约束的门阵列单元库的映射过程，以及图形编辑器中原理图视图的自动电路表示。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Synthesis of combinational circuits from the truth tables in “Kovcheg” CAD design flow

This paper describes the system implemented in “Kovcheg” CAD for integrated circuit design automation. This system allows the user to specify combinational circuits in the form of truth tables. Truth table input values can be specified in automatic mode with a full range of input combinations or in manual mode for specific sets only. The mapping process to the gate array cell library with parameterized constraints as well as the automatic circuit representation of the schematic view in the graphic editor are also described.

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2016 IEEE East-West Design & Test Symposium (EWDTS)

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