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2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)最新文献

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A time-to-digital converter using a multi-phase voltage-controlled oscillator 使用多相压控振荡器的时间-数字转换器
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2010-12-01 DOI: 10.1109/EDSSC.2010.5713764
I. Tang, Shao-Ku Kao
{"title":"A time-to-digital converter using a multi-phase voltage-controlled oscillator","authors":"I. Tang, Shao-Ku Kao","doi":"10.1109/EDSSC.2010.5713764","DOIUrl":"https://doi.org/10.1109/EDSSC.2010.5713764","url":null,"abstract":"This paper presents a time-to-digital converter which employing a multi-phase voltage-controlled oscillator(VCO). The VCO operates at 1GHz clock and generates 16 phases which then expanded up to 64 phases, thus the resolution has expanded to 6 bits. With this technique, any time-based ADC could expand their resolution easily without using a higher frequency.","PeriodicalId":356342,"journal":{"name":"2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134061908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An adaptive edge enhancement algorithm and hardware implementation 一种自适应边缘增强算法及其硬件实现
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2010-12-01 DOI: 10.1109/EDSSC.2010.5713737
Jinkai Long, Xiaoxin Cui, Dunshan Yu
{"title":"An adaptive edge enhancement algorithm and hardware implementation","authors":"Jinkai Long, Xiaoxin Cui, Dunshan Yu","doi":"10.1109/EDSSC.2010.5713737","DOIUrl":"https://doi.org/10.1109/EDSSC.2010.5713737","url":null,"abstract":"In this paper, a novel adaptive edge enhancement algorithm is proposed. A noise reduction algorithm operated in 5×5 block on Y channel is also presented. With the parallel and pipelined structure, the processing time for a single pixel and an image is reduced efficiently. The hardware demo is designed and verified with Xilinx Virtex2 FPGA at frequency 90 MHz.","PeriodicalId":356342,"journal":{"name":"2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128946999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Varying sputtering ambient and annealing gas to optimize the electrical properties of MOS capacitor with HfLaO gate dielectric 改变溅射环境和退火气体以优化HfLaO栅极介质MOS电容器的电学性能
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2010-12-01 DOI: 10.1109/EDSSC.2010.5713772
Q. Tao, P. Lai
{"title":"Varying sputtering ambient and annealing gas to optimize the electrical properties of MOS capacitor with HfLaO gate dielectric","authors":"Q. Tao, P. Lai","doi":"10.1109/EDSSC.2010.5713772","DOIUrl":"https://doi.org/10.1109/EDSSC.2010.5713772","url":null,"abstract":"The impact of sputtering ambient on the properties of HfLaO film is studied by varying the ratio of Ar to O<inf>2</inf>. In order to optimize the electrical performances, the HfLaO film is then annealed in N<inf>2</inf>, NO or NH<inf>3</inf> and evaluated based on Si MOS capacitors. As a result, appropriate ratio of Ar to O<inf>2</inf> during sputtering can increase the permittivity of film while the NH<inf>3</inf> annealing can improve its properties.","PeriodicalId":356342,"journal":{"name":"2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131173566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Frequency multiplier design using BiCMOS-based multiple-peak NDR circuit 基于bicmos多峰NDR电路的倍频器设计
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2010-12-01 DOI: 10.1109/EDSSC.2010.5713683
K. Gan, Ping-Feng Wu, Wu-Yan Shie, Cher-Shiung Tsai, Dong-Shong Liang, Cheng-Hsiung Tsai, W. Yeh
{"title":"Frequency multiplier design using BiCMOS-based multiple-peak NDR circuit","authors":"K. Gan, Ping-Feng Wu, Wu-Yan Shie, Cher-Shiung Tsai, Dong-Shong Liang, Cheng-Hsiung Tsai, W. Yeh","doi":"10.1109/EDSSC.2010.5713683","DOIUrl":"https://doi.org/10.1109/EDSSC.2010.5713683","url":null,"abstract":"We demonstrate a novel frequency multiplier using the negative differential resistance (NDR) circuit based on the standard 0.35 µm BiCMOS technique. This NDR circuit is made of standard Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). We can obtain the three-peak NDR current-voltage (I-V) characteristics by connecting three MOS-HBT-NDR circuits in parallel. These I-V characteristics show high peak-to-valley current ratios with 7.5, 16.8, and 12.1 for three peaks, respectively. Using the folded I-V characteristics, we design a frequency multiplier which can multiply the input saw-tooth signal by a factor of four. The fabrication of this NDR-based frequency multiplier is easier and more convenient compared to the traditional resonant tunneling structure which is implemented by the complicated molecular-beam-epitaxy (MBE) system.","PeriodicalId":356342,"journal":{"name":"2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123943998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A compact model of diode array for Phase Change Memory 一种紧凑的相变存储器二极管阵列模型
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2010-12-01 DOI: 10.1109/EDSSC.2010.5713734
Yanmei Su, Laidong Wang, Ruonan Wang, Xukai Zhang, Yiqun Wei, Wei Wang, Yong Ma, Xinnan Lin, Jin He
{"title":"A compact model of diode array for Phase Change Memory","authors":"Yanmei Su, Laidong Wang, Ruonan Wang, Xukai Zhang, Yiqun Wei, Wei Wang, Yong Ma, Xinnan Lin, Jin He","doi":"10.1109/EDSSC.2010.5713734","DOIUrl":"https://doi.org/10.1109/EDSSC.2010.5713734","url":null,"abstract":"In this paper, a compact diode array model for Phase Change Memory (PCM) application is presented. From the diode array structure and numerical simulation result, a quasi-physical compact model is proposed by combining the classical diode equation and simplified bipolar device formulation. This model results in accurate calculation of different leakage current components with parameter setting. Furthermore, the presented model is an open model structure, and can be applied in different fabrication process with the parameter extraction. All these characteristics make it useful in further study of physical mechanism of carrier transmissions in order to illustrate the device physics of such an array diode device.","PeriodicalId":356342,"journal":{"name":"2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124014701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A large-signal model for GaInP/GaAs heterojunction bipolar transistors GaInP/GaAs异质结双极晶体管的大信号模型
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2010-12-01 DOI: 10.1109/EDSSC.2010.5713730
Yuxia Shi, Yu He, Lin Wang, Yan Wang
{"title":"A large-signal model for GaInP/GaAs heterojunction bipolar transistors","authors":"Yuxia Shi, Yu He, Lin Wang, Yan Wang","doi":"10.1109/EDSSC.2010.5713730","DOIUrl":"https://doi.org/10.1109/EDSSC.2010.5713730","url":null,"abstract":"Based on the Gummel-Poon (GP) model, a simple and physical-based large-signal model for GaInP/GaAs heterojunction bipolar transistors (HBTs) is presented in this paper. We improve the current and transit time model by considering the potential spike effect and negative differential mobility. Different from the UCSD HBT and AgilentHBT models, only 46 parameters are used in our model. The DC characteristics and S-parameter curves are well consistent with the experimental data over a wide range of the operating bias.","PeriodicalId":356342,"journal":{"name":"2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128402848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
WZ-GaN based Quasi-Read ATT diode: A novel high-power THz device with reduced parasitic resistance 基于WZ-GaN的准读ATT二极管:一种降低寄生电阻的新型高功率太赫兹器件
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2010-12-01 DOI: 10.1109/EDSSC.2010.5713780
M. Mukherjee
{"title":"WZ-GaN based Quasi-Read ATT diode: A novel high-power THz device with reduced parasitic resistance","authors":"M. Mukherjee","doi":"10.1109/EDSSC.2010.5713780","DOIUrl":"https://doi.org/10.1109/EDSSC.2010.5713780","url":null,"abstract":"Simulation investigation is carried out on the single drift region and Quasi-Read type hexagonal GaN based IMPATT devices for Terahertz frequency operation. It is observed that Quasi-Read GaN IMPATT may generate a RF power density of ∼43×1010 Wm−2 with an efficiency of 20%, whereas its flat profile counterpart is capable of delivering a power density of 31×1010 Wm−2 with an efficiency of 17%. The total parasitic series resistance, including the effects of ohmic contact resistances, has been found to be a major problem that reduces the RF power output of the THz IMPATTs significantly. The study reveals that the value of RS decreases by 30% as the doping profile of the diode changes from flat to Quasi-Read type with the incorporation of the charge bump. This study establishes the advantages of Quasi-Read type IMPATT over its flat profile counterpart to realize a high-power source in the THz regime.","PeriodicalId":356342,"journal":{"name":"2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128414196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A fast-transient LDO based on buffered flipped voltage follower 基于缓冲翻转电压跟随器的快速瞬态LDO
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2010-12-01 DOI: 10.1109/EDSSC.2010.5713775
Hua Chen, K. Leung
{"title":"A fast-transient LDO based on buffered flipped voltage follower","authors":"Hua Chen, K. Leung","doi":"10.1109/EDSSC.2010.5713775","DOIUrl":"https://doi.org/10.1109/EDSSC.2010.5713775","url":null,"abstract":"In this work, the analysis of the flipped voltage follower (FVF) based single-transistor-control (STC) LDO is given. Two evolved versions of FVF, cascaded FVF (CAFVF) and level shifted FVF (LSFVF), are studied. Then, a buffered FVF (BFVF) for LDO application is proposed, combining the virtues of both CAFVF and LSFVF structures. It alleviates the minimum loading requirement of FVF and the simulation result shows that it has faster transient response and better load regulation.","PeriodicalId":356342,"journal":{"name":"2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128510296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A magnetically shielded instrument for magnetoresistance and noise characterizations of magnetic tunnel junction sensors 一种用于磁隧道结传感器磁阻和噪声表征的磁屏蔽仪器
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2010-12-01 DOI: 10.1109/EDSSC.2010.5713688
Z. Lei, G. Li, P. Lai, P. Pong, W. Egelhoff
{"title":"A magnetically shielded instrument for magnetoresistance and noise characterizations of magnetic tunnel junction sensors","authors":"Z. Lei, G. Li, P. Lai, P. Pong, W. Egelhoff","doi":"10.1109/EDSSC.2010.5713688","DOIUrl":"https://doi.org/10.1109/EDSSC.2010.5713688","url":null,"abstract":"A magnetically shielded setup was developed for characterizing magnetoresistance (MR) and noise properties of magnetic tunneling junction (MTJ) sensors. A mu-metal shielding is installed to avoid the interference of external magnetic disturbance. Both MR curves and noise power spectra of MTJ sensors can be obtained for further data analysis. Moreover, a hard-axis magnetic field can be applied to eliminate the hysteresis and the linear field response of MTJ sensors can be measured. The preliminary measurement results on MTJ sensors are presented to illustrate the characterization capabilities of this setup.","PeriodicalId":356342,"journal":{"name":"2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130231816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
2.4 GHz GaAs PHEMT medium power amplifier for wireless LAN applications 用于无线局域网应用的2.4 GHz GaAs PHEMT中功率放大器
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2010-12-01 DOI: 10.1109/EDSSC.2010.5713754
A. Rasmi, M. R. Che Rose, A. I. Abdul Rahim, A. Marzuki
{"title":"2.4 GHz GaAs PHEMT medium power amplifier for wireless LAN applications","authors":"A. Rasmi, M. R. Che Rose, A. I. Abdul Rahim, A. Marzuki","doi":"10.1109/EDSSC.2010.5713754","DOIUrl":"https://doi.org/10.1109/EDSSC.2010.5713754","url":null,"abstract":"This paper describes the design and measurement of a medium power amplifier (MPA) using 0.15µm GaAs PHEMT technology for wireless application. At 2.4 GHz and 3.0 V of VDS, a fabricated MPA exhibits a P1dB of 15.20 dBm, PAE of 12.70% and gain of 9.70 dB. The maximum current, Imax is 84.40mA and the power consumption for this device is 253.20mW. The die size of this amplifier is 1.2mm × 0.7mm.","PeriodicalId":356342,"journal":{"name":"2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128863932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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