一种自适应边缘增强算法及其硬件实现

2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2010-12-01 DOI:10.1109/EDSSC.2010.5713737

Jinkai Long, Xiaoxin Cui, Dunshan Yu

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引用次数: 2

摘要

本文提出了一种新的自适应边缘增强算法。提出了一种Y信道上5×5块的降噪算法。通过并行和流水线结构，有效地减少了对单个像素和图像的处理时间。硬件演示是用Xilinx Virtex2 FPGA在90 MHz频率下设计和验证的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An adaptive edge enhancement algorithm and hardware implementation

In this paper, a novel adaptive edge enhancement algorithm is proposed. A noise reduction algorithm operated in 5×5 block on Y channel is also presented. With the parallel and pipelined structure, the processing time for a single pixel and an image is reduced efficiently. The hardware demo is designed and verified with Xilinx Virtex2 FPGA at frequency 90 MHz.

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来源期刊

2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)

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