2006 International Symposium on VLSI Design, Automation and Test最新文献_第5页

SoC for COFDM Wireless Communications: Challenges and Opportunities COFDM无线通信的SoC:挑战与机遇

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258125

Chen-Yi Lee, Hsuan-Yu Liu, Chien-Ching Lin

引用次数: 3

Design and Implementation of a 1.2-to-17-GHz UWB SiGe LNA with a Peaking Inductor 带峰值电感的1.2 ~ 17 ghz超宽带SiGe LNA的设计与实现

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258130

Shu-Hui Yen, Yo‐Sheng Lin

引用次数: 2

A Low Power, Transverse Analog FIR Filter as Feed Forward Equalizer in Gigabit Ethernet 千兆位以太网中低功耗横向模拟FIR滤波器的前馈均衡器

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258177

M. B. Vahidfar, O. Shoaei, M. Fardis

引用次数: 1

A Supply-Gating Scheme for Both Data-Retention and Spike-Reduction in Power Management and Test Scheduling 电源管理和测试调度中数据保留和峰值降低的供应门控方案

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258151

Tsung-Chu Huang, J.-C. Tzeng, Yuan-Wei Chao, Ji-Jan Chen, Wei-Ting Liu, Kuen-Jong Lee

引用次数: 2

A Capacitor-free CMOS Low Dropout Regulator with Slew Rate Enhancement 一种具有压转率增强的无电容CMOS低压差稳压器

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258162

Wei-Jen Huang, Sao-Hung Lu, Shen-Iuan Liu

引用次数: 15

Blind Adaptive Mixed-Signal DFE for Gb/s, Multi-Drop, Buses Gb/s多滴总线的盲自适应混合信号DFE

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258165

H. Fredriksson, C. Svensson

引用次数: 4

Design and Implementation of a 1-V Dual-Transformer-Feedback LNA and a 5-GHz-Band Transformer-Feedback VCO 一个1v双变压器反馈LNA和一个5ghz频段变压器反馈VCO的设计与实现

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258178

Yo‐Sheng Lin, Si-Chang Chen, Shu-Bin Chang

引用次数: 0

An All-Digital Phase-Locked Loop with High-Resolution for SoC Applications 高分辨率全数字锁相环，适用于SoC应用

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258161

D. Sheng, Ching-Che Chung, Chen-Yi Lee

引用次数: 42

Gain-based Cell Delay Modeling 基于增益的细胞延迟建模

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258154

S. Nazarian, Massoud Pedram

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引用次数: 0

61.5mW 2048-bit RSA Cryptographic Co-processor LSI based on N bit-wised Modular Multiplier 基于N位模块化乘法器的61.5mW 2048位RSA加密协处理器LSI

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258124

T. Hisakado, N. Kobayashi, S. Goto, T. Ikenaga, K. Higashi, I. Kitao, Y. Tsunoo

{"title":"61.5mW 2048-bit RSA Cryptographic Co-processor LSI based on N bit-wised Modular Multiplier","authors":"T. Hisakado, N. Kobayashi, S. Goto, T. Ikenaga, K. Higashi, I. Kitao, Y. Tsunoo","doi":"10.1109/VDAT.2006.258124","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258124","url":null,"abstract":"RSA, one of the public key cryptographies, is the most widely used for a wide variety of information systems. Especially, a compact, high-performance RSA LSI is highly desired for mobile applications, such as a smart card and a cellular phone. This paper describes a RSA cryptography co-processor LSI. It can process up to 2048-bit key data, which is required to guarantee the high security level of RSA. Although a large computational complexity is required to process 2048-bit RSA, our proposed N bit-wise modular multiplier based on Montgomery multiplication algorithm enables to reduce 25% circuit amount compared with the conventional one. A chip capable of operating at 60 MHz was fabricated using 0.18 mum TSMC CMOS technology. A total of 98.5 k gates (incl. SRAM and I/O modules) have been integrated into a 2.2 times 2.2 mm chip. Evaluation result with IC test system shows that power dissipation is 61.5 mW when 2048-bit RSA processing is operated at 40 MHz. This RSA LSI will make a significant contribution to the development of compact, high-performance secure information systems","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134100818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4