{"title":"Design and Implementation of a 1-V Dual-Transformer-Feedback LNA and a 5-GHz-Band Transformer-Feedback VCO","authors":"Yo‐Sheng Lin, Si-Chang Chen, Shu-Bin Chang","doi":"10.1109/VDAT.2006.258178","DOIUrl":null,"url":null,"abstract":"In this paper, a dual-transformer-feedback LNA architecture is proposed. One of the transformer-feedback is for reducing the supply voltage, the other is for improving the linearity of the LNA. A 1-V fully integrated dual-transformer-feedback LNA was implemented in standard 0.18 mum CMOS process to demonstrate the idea. The LNA exhibits voltage gain of 11.5 dB, input return loss (S11) of -11 dB, reverse isolation (S12) of -29.9 dB, NF of 2.65 dB, and IIP3 of 7 dBm at 2.4 GHz. The chip area is only 0.28 mm2, excluding the test pads. This LNA drains 15.3 mA current at supply voltage of 1 V, i.e. it consumes 15.3 mW power. Besides, a 1.2 V 5-GHz band transformer-feedback VCO was also implemented. The VCO exhibits tuning range of 165 MHz (5.449 - 5.614 GHz for Vtune = 0-0.7 V), phase noise of -97 dBc/Hz at 1 MHz offset from 5.6 GHz. The chip area is only 0.525 mm2, excluding the test pads. The VCO consumes 8.82 mW power","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2006.258178","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, a dual-transformer-feedback LNA architecture is proposed. One of the transformer-feedback is for reducing the supply voltage, the other is for improving the linearity of the LNA. A 1-V fully integrated dual-transformer-feedback LNA was implemented in standard 0.18 mum CMOS process to demonstrate the idea. The LNA exhibits voltage gain of 11.5 dB, input return loss (S11) of -11 dB, reverse isolation (S12) of -29.9 dB, NF of 2.65 dB, and IIP3 of 7 dBm at 2.4 GHz. The chip area is only 0.28 mm2, excluding the test pads. This LNA drains 15.3 mA current at supply voltage of 1 V, i.e. it consumes 15.3 mW power. Besides, a 1.2 V 5-GHz band transformer-feedback VCO was also implemented. The VCO exhibits tuning range of 165 MHz (5.449 - 5.614 GHz for Vtune = 0-0.7 V), phase noise of -97 dBc/Hz at 1 MHz offset from 5.6 GHz. The chip area is only 0.525 mm2, excluding the test pads. The VCO consumes 8.82 mW power