A Supply-Gating Scheme for Both Data-Retention and Spike-Reduction in Power Management and Test Scheduling

Abstract

Power gating using sleep transistors is a trend for power management and test scheduling in the deep-submicron and even nanometer resolutions. This paper develops a sleep transistor allocation structure that can not only reduce the spike-time product with data retention but also balance the noise margins and timing in active mode. A switching activity based model is developed as a heuristics for sleep transistor clustering. Under the proposed model, the spike reduction can be up to 83% in average