2006 International Symposium on VLSI Design, Automation and Test最新文献_第4页

V-Band CMOS Differential-type Injection Locked Frequency Dividers v波段CMOS差分型注入锁定分频器

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258187

F. Huang, Y. Chan

{"title":"V-Band CMOS Differential-type Injection Locked Frequency Dividers","authors":"F. Huang, Y. Chan","doi":"10.1109/VDAT.2006.258187","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258187","url":null,"abstract":"While the operation frequency of the wireless and the wire-used modern communication systems has being extended to millimeter-wave band, the timing circuits also become important for the low-cost and performance concerns, such as synthesizer or frequency divider. As the millimeter-wave wireless local area network (WLAN) transmitting a digital modulated data upon a carrier frequency through a antenna, is proposed to either obtain a broadcasting service in local area or provide the flexible data access. For the requirement of synchronization, hence the high speed and high frequency dividers/prescalars up to 60 GHz may be employed in phase-locked loop (PLL). Moreover, the power consumption and the low noise features in the divider circuits are also the major concerns. Conventional common-mode logic (CML) dividers are difficult to push the maximum operation frequency to over the microwave range due to its limitation by the cut-off frequency fT, regardless it reaches a wide dividing range. Extreme high power consumption is also the disadvantage for CML approach. Thus to fulfil the low power dissipation dividers, the LC-type injection-locked frequency dividers (ILFD) have been proposed and being used in PLL or clock-data recovery (CDR) circuits as stated in H. R. Rategh et al. (1999). The CMOS submicron techniques have been progressed to a proper high frequency divider design. In this work, there are two 60 GHz ILFDs have been realized by using the CMOS 0.18mum 1P6M technology, in which contain the self-oscillation frequencies of 30 GHz and 15 GHz respectively for a divided-by 2 or 4 operation. Both ILFDs demonstrate the improved locking ranges using a self-oscillation frequency tuning and a 0/180deg single-to-differential power divider with low dc power consumptions","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125426560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Power-On Current Control In Sleep Transistor Implementations 休眠晶体管的上电电流控制实现

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258174

D. Howard, K. Shi

引用次数: 7

A VLSI Layout Legalization Technique Based on a Graph Fixing Algorithm 一种基于图固定算法的VLSI版图合法化技术

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258148

S.D. Wu, C. Tsai, M. Yang

{"title":"A VLSI Layout Legalization Technique Based on a Graph Fixing Algorithm","authors":"S.D. Wu, C. Tsai, M. Yang","doi":"10.1109/VDAT.2006.258148","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258148","url":null,"abstract":"This paper describes a novel graph fixing algorithm which can be used to fix the design constraint violations for a VLSI layout. Layouts are designed so that the process design rule and user specified constraints must be satisfied. Custom layout methodologies and process design rule migration activities introduce rule and constraint violations in layouts. Traditionally, layout compaction technique based on minimal area criterion is used to solve layout constraint violation problem. Unfortunately such layout compaction technique often fail in real designs since the layout often changed significantly and resulted in circuit performance degeneracy after layout compaction. Recently, a minimum layout perturbation was proposed to overcome the aforementioned drawback. The layout legalization was formulated as a linear programming problem which objective function was the summation of the perturbation of shapes. Such works reduced the impact on circuit performance greatly. In this paper, based on the concept of minimum layout perturbation, a more efficient graph fixing algorithm is proposed to solve layout legalization problem. This algorithm has been implemented as a part of Lakertrade AutoCorrect function and demonstrated the efficiency and feasibility for several real designs","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114627121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

System Redundancy; A Means of Improving Process Variation Yield Degradation in Memory Arrays 系统冗余;一种改善存储器阵列工艺变化良率退化的方法

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258144

A. Eltawil, F. Kurdahi

引用次数: 8

A High-Speed Baseband Receiver for MIMO OFDM Based WLAN 一种基于MIMO OFDM的无线局域网高速基带接收机

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258172

Tsung-Hsueh Lee, Jing-Siang Jhuang, T. Chiueh

引用次数: 1

The Column Driver Circuit Design for Passive Organic Electroluminescence Display 无源有机电致发光显示柱驱动电路设计

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258182

Wen-Yaw Chung, Yu-Chien Tseng, Yu-Wen Chen, Chih-Jen Yen

引用次数: 0

A 0.18 μm CMOS Prototype of COFDM Demodulator for European DVB-T Standard 欧洲DVB-T标准COFDM解调器0.18 μm CMOS样机

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258126

Chua-Chin Wang, Jian-Ming Huang, Yung-Mu Tseng, Chih-Yi Chang

引用次数: 0

Challenges on Low-Power Platform Design for Real-World Wireless Sensing Applications 面向现实世界无线传感应用的低功耗平台设计挑战

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258139

P. Chou

引用次数: 4

High performance on-chip interconnect system supporting fast SoC generation 支持快速SoC生成的高性能片上互连系统

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258122

O. Goren, Y. Netanel

引用次数: 4

A Low-Power and Compact Sigma-Delta Voice-band Codec in a 0.18-μm CMOS Technology 基于0.18 μm CMOS技术的低功耗、紧凑型Sigma-Delta语音带编解码器

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258109

D. Quoc-Dang Ho, Chin Chang, J. Rathore, L. D'Souza, Yuwen Swei, Kuan-Dar Chen, Jyhfong Lin

引用次数: 0