System Redundancy; A Means of Improving Process Variation Yield Degradation in Memory Arrays

Abstract

This paper addresses the fact that memory yield is the dominant issue affecting overall yield in nano-scale devices. It illustrates that by treating yield as a system design parameter, tremendous gains in effective chip yield can be achieved. The techniques outlined are especially suited for applications that have inherent system redundancy such as wireless communication. In that context, the paper illustrates a that system redundancy can easily tolerate up to 1% bit errors in memory while meeting system specifications such as bit error rate (BER) metrics