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Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit最新文献

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An analysis of shorts in CMOS standard cell circuits CMOS标准单元电路中的短路分析
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-10-01 DOI: 10.1109/ASIC.1994.404540
A. Jee, F. Ferguson
{"title":"An analysis of shorts in CMOS standard cell circuits","authors":"A. Jee, F. Ferguson","doi":"10.1109/ASIC.1994.404540","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404540","url":null,"abstract":"In order to provide high levels of IC quality, we must be able to detect the presence of a very high percentage of the defects that may occur in circuits. Our long term goal is to address this problem by developing guidelines to design circuits to be more easily tested without requiring complex fault models or testing techniques. This paper is a first step towards this goal. This paper contains data on which shorting defects are most likely to occur in CMOS standard cell circuits and which are most likely to not be detected by standard testing methods.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127699383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A flexible repetitive CSD code filter processor unit in CMOS CMOS中灵活的重复CSD码滤波处理器单元
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404562
S. Hentschke, A. Herrfeld, N. Reifschneider, D. Forster, M. Heinemann, A. Wicke
{"title":"A flexible repetitive CSD code filter processor unit in CMOS","authors":"S. Hentschke, A. Herrfeld, N. Reifschneider, D. Forster, M. Heinemann, A. Wicke","doi":"10.1109/ASIC.1994.404562","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404562","url":null,"abstract":"We introduce a filter processor unit that realizes digital nonrecursive (FIR) and recursive (IIR) filtering with optimal selectable coefficient, data wordlength and filter order. This flexibility is achieved by combination of four identical filter modules. The design is carried out in a 1.0 /spl mu/ CMOS process; additionally a multiplier-free second order /spl Sigma//spl Delta/-modulator is implemented. It occupies a chip area of 87 mm/sup 2/.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115704560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Recent developments in simulation 仿真的最新发展
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404550
A. Davis
{"title":"Recent developments in simulation","authors":"A. Davis","doi":"10.1109/ASIC.1994.404550","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404550","url":null,"abstract":"This tutorial presents an overview of recent developments in simulation. It will review the traditional SPICE techniques then introduce the more recent work including relaxation, waveform relaxation and asymptotic waveform evaluation.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124274008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low voltage, low power 13-bit linear voice codec with programmable analogue frontend 低电压，低功耗13位线性语音编解码器与可编程模拟前端
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404556
D. Strle, A. Pletersek, K. Riedmueller, T. Karema
{"title":"Low voltage, low power 13-bit linear voice codec with programmable analogue frontend","authors":"D. Strle, A. Pletersek, K. Riedmueller, T. Karema","doi":"10.1109/ASIC.1994.404556","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404556","url":null,"abstract":"A low-voltage, low-power 13-bit linear voice codec has been developed and implemented in 1.2 /spl mu/m CMOS technology. At single supply voltage greater than 2.6 V and power dissipation of 20 mW it fulfils or exceeds all NET33 recommendations for digital handset terminals. Active area for a complete codec is 29 mm/sup 2/. It can be used as an analogue frontend for DSP, digital cordless telephone, a digital cellular telephone or a digital answering machine.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127162253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Using HYPER to teach datapath design techniques in an ASIC design course 在ASIC设计课程中使用HYPER教授数据路径设计技术
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404576
R. B. Reese, Drawer Ee
{"title":"Using HYPER to teach datapath design techniques in an ASIC design course","authors":"R. B. Reese, Drawer Ee","doi":"10.1109/ASIC.1994.404576","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404576","url":null,"abstract":"HYPER is a high level synthesis tool available from UC Berkeley for real-time, datapath intensive architectures such as those found in digital signal processing and video imaging applications. We have used HYPER as an adjunct tool in our ASIC design course for illustrating area versus time versus power tradeoffs in datapath design. These design tradeoffs can be explored via HYPER's wide range of transformation capabilities which include pipelining, retiming, constant multiplication expansion, time-loop unrolling and various algebraic law transformations.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114917197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VHDL-A: analog extension to VHDL VHDL- a: VHDL的模拟扩展
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404586
R. Shi, E. Christen, P. Liebmann, S. Krolikoski, W. Zhou
{"title":"VHDL-A: analog extension to VHDL","authors":"R. Shi, E. Christen, P. Liebmann, S. Krolikoski, W. Zhou","doi":"10.1109/ASIC.1994.404586","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404586","url":null,"abstract":"VHDL is an IEEE standardized language for the description and simulation of digital circuits and systems. Originally developed in the early 1980s, VHDL has achieved great success in electronic design automation, and is emerging as an indispensable tool to deal with complex ASIC system design. However, VHDL is primarily designed to model digital behavior. Nowadays, a majority of ASIC designs contain both analog and digital elements. Also, ultra-fast digital designs are composed of cells and interconnects that exhibit primarily analog character. Full system verification of an ASIC design needs modeling of its application environments, which are usually non-electrical such as mechanical and thermal. This paper describes VHDL-A: an IEEE effort towards a standardized analog extension of VHDL to address these needs. The emphasis of this paper is on main language concepts and features and how they can be used to describe and simulate mixed analog and digital designs.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122639779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A fast Reed-Solomon and cyclic redundancy check encoding algorithm for optical disk error control 一种用于光盘误差控制的快速Reed-Solomon和循环冗余校验编码算法
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404565
Robert Kao, V.L. Gibbs
{"title":"A fast Reed-Solomon and cyclic redundancy check encoding algorithm for optical disk error control","authors":"Robert Kao, V.L. Gibbs","doi":"10.1109/ASIC.1994.404565","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404565","url":null,"abstract":"Error control schemes have been applied to insure data integrity in high density digital mass storage medium. Specifically, optical disk applications are especially susceptible to various types of disturbances, and therefore require higher levels of error detection and correction capabilities. In this paper, efficient algorithms for implementing Cyclic Redundancy Check (CRC) and Reed-Solomon (RS) code encoding are evaluated using a top-down design methodology. The results show the Parallel Encoding Method provides highest performance.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122912244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A self timed interrupt controller: a case study in asynchronous micro-architecture design 自定时中断控制器:异步微架构设计的案例研究
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404555
A. De Gloria, P. Faraboschi, M. Olivieri
{"title":"A self timed interrupt controller: a case study in asynchronous micro-architecture design","authors":"A. De Gloria, P. Faraboschi, M. Olivieri","doi":"10.1109/ASIC.1994.404555","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404555","url":null,"abstract":"We report the results of the design and layout simulation of an interrupt controller dedicated to the SGS-Thomson ST9 microprocessor family. The unit is composed of a delay insensitive local control-path and a synchronous local data-path for priority computations. The local control-path is automatically synthesised out of an Occam algorithmic specification, while the local data-path is made up of conventional hardware units. Layout simulation shows that the average time for an interrupt to be served is reduced to 28%.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123359967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A methodology for design verification 设计验证的方法
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404568
E. Hu, B. Yeh, T. Chan
{"title":"A methodology for design verification","authors":"E. Hu, B. Yeh, T. Chan","doi":"10.1109/ASIC.1994.404568","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404568","url":null,"abstract":"Recent advancements in design automation tools have helped to shorten the design time for many ASICs. The functional verification of these ASICs, however, remains a wholly labor intensive and sequential task. This paper documents a parallel flow methodology that addresses the problem with a different approach to resource distribution for verification. Such a distribution allows for more time and resources to be dedicated to the verification task while still supporting a shortened design cycle.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126557559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An analog VLSI neural network for real-time image processing in industrial applications 模拟VLSI神经网络的实时图像处理在工业应用
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404614
M. Valle, M. Onorato, F. Oddone, D. Caviglia, G. Bisio
{"title":"An analog VLSI neural network for real-time image processing in industrial applications","authors":"M. Valle, M. Onorato, F. Oddone, D. Caviglia, G. Bisio","doi":"10.1109/ASIC.1994.404614","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404614","url":null,"abstract":"In this paper we present an analog VLSI architecture that implements a neural network for image processing in industrial environment. The analog architecture is highly modular and operates in real time. The circuit implementation is based on simple and effective circuit primitives. Special care has been devoted to the analysis of the linearity and the precision of computation. A test chip, implementing the filtering stage of the architecture, has been designed and realized.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131243103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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