A flexible repetitive CSD code filter processor unit in CMOS

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI:10.1109/ASIC.1994.404562

S. Hentschke, A. Herrfeld, N. Reifschneider, D. Forster, M. Heinemann, A. Wicke

引用次数: 6

Abstract

We introduce a filter processor unit that realizes digital nonrecursive (FIR) and recursive (IIR) filtering with optimal selectable coefficient, data wordlength and filter order. This flexibility is achieved by combination of four identical filter modules. The design is carried out in a 1.0 /spl mu/ CMOS process; additionally a multiplier-free second order /spl Sigma//spl Delta/-modulator is implemented. It occupies a chip area of 87 mm/sup 2/.<>

查看原文本刊更多论文

CMOS中灵活的重复CSD码滤波处理器单元

介绍了一种滤波处理器单元，实现了具有最优可选系数、数据字长和滤波阶数的数字非递归滤波(FIR)和递归滤波(IIR)。这种灵活性是通过四个相同的过滤器模块的组合实现的。设计是在1.0 /spl mu/ CMOS工艺下进行的;另外，实现了一个无乘法器的二阶/spl σ //spl δ /调制器。它的芯片面积为87毫米/平方英尺。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit

自引率

0.00%

发文量