{"title":"设计验证的方法","authors":"E. Hu, B. Yeh, T. Chan","doi":"10.1109/ASIC.1994.404568","DOIUrl":null,"url":null,"abstract":"Recent advancements in design automation tools have helped to shorten the design time for many ASICs. The functional verification of these ASICs, however, remains a wholly labor intensive and sequential task. This paper documents a parallel flow methodology that addresses the problem with a different approach to resource distribution for verification. Such a distribution allows for more time and resources to be dedicated to the verification task while still supporting a shortened design cycle.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A methodology for design verification\",\"authors\":\"E. Hu, B. Yeh, T. Chan\",\"doi\":\"10.1109/ASIC.1994.404568\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recent advancements in design automation tools have helped to shorten the design time for many ASICs. The functional verification of these ASICs, however, remains a wholly labor intensive and sequential task. This paper documents a parallel flow methodology that addresses the problem with a different approach to resource distribution for verification. Such a distribution allows for more time and resources to be dedicated to the verification task while still supporting a shortened design cycle.<<ETX>>\",\"PeriodicalId\":354289,\"journal\":{\"name\":\"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-09-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1994.404568\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1994.404568","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Recent advancements in design automation tools have helped to shorten the design time for many ASICs. The functional verification of these ASICs, however, remains a wholly labor intensive and sequential task. This paper documents a parallel flow methodology that addresses the problem with a different approach to resource distribution for verification. Such a distribution allows for more time and resources to be dedicated to the verification task while still supporting a shortened design cycle.<>
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