M. Valle, M. Onorato, F. Oddone, D. Caviglia, G. Bisio
{"title":"模拟VLSI神经网络的实时图像处理在工业应用","authors":"M. Valle, M. Onorato, F. Oddone, D. Caviglia, G. Bisio","doi":"10.1109/ASIC.1994.404614","DOIUrl":null,"url":null,"abstract":"In this paper we present an analog VLSI architecture that implements a neural network for image processing in industrial environment. The analog architecture is highly modular and operates in real time. The circuit implementation is based on simple and effective circuit primitives. Special care has been devoted to the analysis of the linearity and the precision of computation. A test chip, implementing the filtering stage of the architecture, has been designed and realized.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"135 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"An analog VLSI neural network for real-time image processing in industrial applications\",\"authors\":\"M. Valle, M. Onorato, F. Oddone, D. Caviglia, G. Bisio\",\"doi\":\"10.1109/ASIC.1994.404614\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present an analog VLSI architecture that implements a neural network for image processing in industrial environment. The analog architecture is highly modular and operates in real time. The circuit implementation is based on simple and effective circuit primitives. Special care has been devoted to the analysis of the linearity and the precision of computation. A test chip, implementing the filtering stage of the architecture, has been designed and realized.<<ETX>>\",\"PeriodicalId\":354289,\"journal\":{\"name\":\"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit\",\"volume\":\"135 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-09-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1994.404614\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1994.404614","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An analog VLSI neural network for real-time image processing in industrial applications
In this paper we present an analog VLSI architecture that implements a neural network for image processing in industrial environment. The analog architecture is highly modular and operates in real time. The circuit implementation is based on simple and effective circuit primitives. Special care has been devoted to the analysis of the linearity and the precision of computation. A test chip, implementing the filtering stage of the architecture, has been designed and realized.<>