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Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit最新文献

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Simultaneous switch noise modeling for high performance ASIC 高性能ASIC的同步开关噪声建模
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404547
B. Andresen, R. Martin, S. Keeney, S. Schenck, R. W. Phelps
{"title":"Simultaneous switch noise modeling for high performance ASIC","authors":"B. Andresen, R. Martin, S. Keeney, S. Schenck, R. W. Phelps","doi":"10.1109/ASIC.1994.404547","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404547","url":null,"abstract":"Texas Instruments ASIC Division (TI) has developed a highly accurate and flexible statistical characterization technique using equations to predict output switching noise. A 21-term polynomial equation is described which accurately predicts the number of ground and V/sub cc/ pins required for a given design as nonlinear functions of the number of outputs switching simultaneously, the number of active outputs which are not switching, the ground or V/sub cc/ noise levels allowed, the package pin inductances and transmission line characteristics of the loads. The accuracy and flexibility of this technique is contrasted with traditional, less sophisticated methods.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114729887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A VLSI design and cost analysis of broadband ATM switch elements 宽带ATM交换元件的VLSI设计与成本分析
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404546
H. Shi, D. Ennis, S. Fernández, C. Zukowski, O. Wing
{"title":"A VLSI design and cost analysis of broadband ATM switch elements","authors":"H. Shi, D. Ennis, S. Fernández, C. Zukowski, O. Wing","doi":"10.1109/ASIC.1994.404546","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404546","url":null,"abstract":"This paper presents a design of a combined input/output-buffered ATM switch. Its basic elements are implemented using CMOS technology and HDL-based design. The impact of the system and implementation parameters on silicon area and transistor count is studied in detail for the first time, and VLSI cost functions are proposed. The purpose of this paper is to provide a VLSI cost analysis for a novel switch design optimization methodology, proposed in another paper.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116677523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
ASIC design and implementation of an associative memory processor for syntactic recognition 用于语法识别的联想记忆处理器的ASIC设计与实现
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404559
Nelson Correa, Antonio Garcia, Hugo Burbano, William Ricaurte
{"title":"ASIC design and implementation of an associative memory processor for syntactic recognition","authors":"Nelson Correa, Antonio Garcia, Hugo Burbano, William Ricaurte","doi":"10.1109/ASIC.1994.404559","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404559","url":null,"abstract":"This paper presents the ASIC design and implementation of a special purpose processor for syntactic recognition of context-free languages. The machine is an associative processor that takes advantage of the single-instruction multiple-data stream (SIMD) parallel processing capability of a content-addressable memory (CAM), designed to operate as a coprocessor in systems with an I.S.A. bus (IBM PC/AT). The processor is designed and implemented with multiple ASIC components, including both a full-custom content-addressable memory device and multiple Programmable Logic Devices (FPGA/PLD).<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123623127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Graphical specification of digital systems using interval temporal logic 使用间隔时间逻辑的数字系统的图形规范
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404589
M. Hadjinicolaou, G. Musgrave, R. B. Hughes
{"title":"Graphical specification of digital systems using interval temporal logic","authors":"M. Hadjinicolaou, G. Musgrave, R. B. Hughes","doi":"10.1109/ASIC.1994.404589","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404589","url":null,"abstract":"This paper considers by means of an example how the behaviour of a digital circuit can be synthesised from a detail specification described in Interval Temporal Logic (ITL) which itself can be derived from a timing diagram.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130032877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A dual-channel analog servo-signal processor for 13 Gb tape drives 用于13 Gb磁带驱动器的双通道模拟伺服信号处理器
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404615
S. Narayan, H. Klein
{"title":"A dual-channel analog servo-signal processor for 13 Gb tape drives","authors":"S. Narayan, H. Klein","doi":"10.1109/ASIC.1994.404615","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404615","url":null,"abstract":"This paper describes the first dual-channel analog signal processor for servo control in a 13 Gbyte QIC tape drive systems. The highly programmable low-power, low-cost CMOS IC provides 12 bit accuracy employing sophisticated real-time peak-detection, error correction, and calibration. It provides both analog and digital servo information, servo motor control and built-in analog test capability. Innovative circuit implementations presented here include a high-bandwidth VGA and a peak-detector with clock recovery which removes the need for on-chip PLLs. Behavioral modeling of the entire chip was used to ensure system integrity.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129525324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A single-chip multiprocessor DSP solution for communications applications 用于通信应用的单片多处理器DSP解决方案
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404525
D. Regenold
{"title":"A single-chip multiprocessor DSP solution for communications applications","authors":"D. Regenold","doi":"10.1109/ASIC.1994.404525","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404525","url":null,"abstract":"This paper presents an overview of an architecture for a single-chip multiprocessor DSP solution for communications applications. The integrated circuit was designed to handle the protocol and data-pump functions necessary to implement high-speed modem and audio tasks. The chip consists of a 186 microcontroller with two Digital Signal Processing (DSPs) coprocessors. It interfaces with a standard 186 bus and has a port for communicating with a custom CODEC, the 80127.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124636352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A modular, high performance, 2 /spl mu/m CCD-BiCMOS process technology for application specific image sensors and image sensor systems on a chip 一种模块化，高性能，2 /spl mu/m的CCD-BiCMOS工艺技术，用于特定应用的图像传感器和芯片上的图像传感器系统
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404542
R. Guidash, P. Lee, J. Andrus, A. S. Ciccarelli, H. J. Erhardt, J. Fischer, E. Meisenzahl, R. Philbrick, G. Ting
{"title":"A modular, high performance, 2 /spl mu/m CCD-BiCMOS process technology for application specific image sensors and image sensor systems on a chip","authors":"R. Guidash, P. Lee, J. Andrus, A. S. Ciccarelli, H. J. Erhardt, J. Fischer, E. Meisenzahl, R. Philbrick, G. Ting","doi":"10.1109/ASIC.1994.404542","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404542","url":null,"abstract":"A 2 /spl mu/m BiCMOS process module has been developed for incorporation into existing charge-coupled device (CCD) image sensor processes. The modular process architecture allows integration of CMOS, NPN bipolar or BiCMOS circuits without affecting the baseline CCD characteristics, and enables on-chip integration of desired analog and digital circuit functions with the image sensor. To our knowledge this is the first demonstration of high performance CCD, 2 /spl mu/m CMOS, and an isolated vertical NPN integrated on the same chip.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126979137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Low power via reduced switching activity and its application to PLAs 降低开关活度的低功耗及其在PLAs中的应用
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404600
R. Hossain, A. Albicki
{"title":"Low power via reduced switching activity and its application to PLAs","authors":"R. Hossain, A. Albicki","doi":"10.1109/ASIC.1994.404600","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404600","url":null,"abstract":"In this paper a systematic study of the expected switching activity (ESA) in combinational logic circuits is presented. Based on this study, a technique for reducing the power dissipation in two-level combinational logic is presented. The paper also discusses the switching activity in multilevel circuits.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"8 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127513858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A proposed training curriculum in ASIC design 建议的ASIC设计培训课程
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404574
M.M. Farhoomand
{"title":"A proposed training curriculum in ASIC design","authors":"M.M. Farhoomand","doi":"10.1109/ASIC.1994.404574","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404574","url":null,"abstract":"In this paper we propose comprehensive curriculum of training courses in the area of ASIC design. The curriculum consists of six program areas containing intensive courses, each ranging from two to four days in duration. The majority of the courses are hands-on, where the students work on PCs or workstations. All include in-class exercises to reinforce the topics learned. There are several points of entry into the curriculum depending on the background and needs of the individual. The curriculum serves to bring the students \"up-to-speed\" in ASIC design knowledge and minimize the on-the-job learning curve.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132629028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Computer-aided design-verification vector generation 计算机辅助设计验证向量生成
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI: 10.1109/ASIC.1994.404590
C. Stroud, M. Ericson
{"title":"Computer-aided design-verification vector generation","authors":"C. Stroud, M. Ericson","doi":"10.1109/ASIC.1994.404590","DOIUrl":"https://doi.org/10.1109/ASIC.1994.404590","url":null,"abstract":"This paper describes the features and usage of a CAD tool that assists ASIC designers in the generation of design-verification vectors. The designer describes the ASIC interfaces as well as the desired operations to be performed in an assembly language format from which the CAD tool generates the actual input stimulus and timing relationships for the design-verification simulation.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134325373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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