{"title":"A dual-channel analog servo-signal processor for 13 Gb tape drives","authors":"S. Narayan, H. Klein","doi":"10.1109/ASIC.1994.404615","DOIUrl":null,"url":null,"abstract":"This paper describes the first dual-channel analog signal processor for servo control in a 13 Gbyte QIC tape drive systems. The highly programmable low-power, low-cost CMOS IC provides 12 bit accuracy employing sophisticated real-time peak-detection, error correction, and calibration. It provides both analog and digital servo information, servo motor control and built-in analog test capability. Innovative circuit implementations presented here include a high-bandwidth VGA and a peak-detector with clock recovery which removes the need for on-chip PLLs. Behavioral modeling of the entire chip was used to ensure system integrity.<<ETX>>","PeriodicalId":354289,"journal":{"name":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1994.404615","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper describes the first dual-channel analog signal processor for servo control in a 13 Gbyte QIC tape drive systems. The highly programmable low-power, low-cost CMOS IC provides 12 bit accuracy employing sophisticated real-time peak-detection, error correction, and calibration. It provides both analog and digital servo information, servo motor control and built-in analog test capability. Innovative circuit implementations presented here include a high-bandwidth VGA and a peak-detector with clock recovery which removes the need for on-chip PLLs. Behavioral modeling of the entire chip was used to ensure system integrity.<>