降低开关活度的低功耗及其在PLAs中的应用

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit Pub Date : 1994-09-19 DOI:10.1109/ASIC.1994.404600

R. Hossain, A. Albicki

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引用次数: 12

摘要

本文系统地研究了组合逻辑电路的预期开关活动。在此基础上，提出了一种降低两级组合逻辑的功耗的方法。本文还讨论了多电平电路中的开关活动

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Low power via reduced switching activity and its application to PLAs

In this paper a systematic study of the expected switching activity (ESA) in combinational logic circuits is presented. Based on this study, a technique for reducing the power dissipation in two-level combinational logic is presented. The paper also discusses the switching activity in multilevel circuits.<>

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Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit

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