A VLSI design and cost analysis of broadband ATM switch elements

Abstract

This paper presents a design of a combined input/output-buffered ATM switch. Its basic elements are implemented using CMOS technology and HDL-based design. The impact of the system and implementation parameters on silicon area and transistor count is studied in detail for the first time, and VLSI cost functions are proposed. The purpose of this paper is to provide a VLSI cost analysis for a novel switch design optimization methodology, proposed in another paper.<>