Proceedings of 1994 IEEE Symposium on VLSI Circuits最新文献_第3页

3. Ogb/s, 272mw, 8:1 Multiplexer And 4.1gb/s, 388mw, 1:8 Demultiplexer 3.。Ogb/s, 272mw, 8:1复用器和4.1gb/s, 388mw, 1:8复用器

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI: 10.1109/VLSIC.1994.586247

K. Ueda, N. Sasaki, H. Sato, S. Kubo, K. Mashiko

{"title":"3. Ogb/s, 272mw, 8:1 Multiplexer And 4.1gb/s, 388mw, 1:8 Demultiplexer","authors":"K. Ueda, N. Sasaki, H. Sato, S. Kubo, K. Mashiko","doi":"10.1109/VLSIC.1994.586247","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586247","url":null,"abstract":"I . INTRODUCTION Optical transmission systems require multiplexer and demultiplexer chips as the major ingredients. There have been proposed and realized several architectures for multiplexers and demultiplexers. Such as the shift resister architecture, the interleaved architecture, the series gated architecture, and so on. In general, these previous architectures have aimed at high speed operation rather than low power dissipation. In multiplexers, the series gated architecture is effective in reducing power dissipation because the series gate can implement complex logic with fewer current sources. However, the architecture requires the 3-level for the series gate [l]. Thus it is difficult to lower the supply voltage for multiplexers. Furthermore, the architecture requires larger current to drive the 3-level series gate at high speed. On the other hand, the interleaved architecture is widely used in demultiplexers. In this architecture, conversion from serial to parallel data requires the lst, 2nd and 3rd stage flipflops [2]. This requires a large amount of hardware and therefore consumes much power. In this paper, 8:l multiplexer and 1% demultiplexer chips with low power dissipation are described. The multiplexer chip adopts the modified series gated architecture, while the demultiplexer chip adopts the modified interleaved architecture.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124231903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A 64-site Multiplexed Low-profile Neural Probe With On-chip Cmos Circuitry 基于片上Cmos电路的64位复用低姿态神经探针

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI: 10.1109/VLSIC.1994.586234

Changhyun Kim, K. Wise

引用次数: 9

A Programmable Clock Generator Using Noise Shaping And Its Application In A Switched-capacitor Filter 基于噪声整形的可编程时钟发生器及其在开关电容滤波器中的应用

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI: 10.1109/VLSIC.1994.586238

P. Hurst, B. Rothenberg

引用次数: 0

Multiplexer-Based Architecture for High-Density, Low-Power Gate Arrays 基于多路复用器的高密度低功耗门阵列架构

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI: 10.1109/VLSIC.1994.586198

R. Landers, S. Mahant-Shetti, C. Lemonds

引用次数: 5

Power Dissipation Measurements on Recovered Energy Logic 回收能量逻辑的功耗测量

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI: 10.1109/VLSIC.1994.586170

R. T. Hinman, F. Martin, Schlecht

引用次数: 21

A Digital Self Compensation Circuit for High Speed D/a Converters 用于高速数模转换器的数字自补偿电路

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI: 10.1109/VLSIC.1994.586160

Ook Kim, Jungwook Yang, Suk-ki Kim, Wonchan Kim

引用次数: 0

A Novel Synchronous Timing Control For 200mhz Mega-bits BiCMOS SRAM at 2.5V Operation 一种新的2.5V工作200mhz兆比特BiCMOS SRAM同步定时控制方法

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI: 10.1109/VLSIC.1994.586242

A. Suzuki, H. Kato

引用次数: 1

Automatic Voltage-swing Reduction (avr) Scheme For Ultra Low Power Drams 超低功耗dram的自动减压(avr)方案

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI: 10.1109/VLSIC.1994.586229

M. Tsukude, M. Hirose, S. Tomishima, T. Tsuruda, T. Yamagata, K. Arimoto, K. Fujishima

引用次数: 8

A 15- 150mhz, All-Digital Phase-Locked Loop with 50-Cycle Lock Time for High-Performance Low-Power Microprocessors 用于高性能低功耗微处理器的15- 150mhz全数字锁相环，锁相时间为50个周期

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI: 10.1109/VLSIC.1994.586199

J. Lundberg, E. Nuckolls

{"title":"A 15- 150mhz, All-Digital Phase-Locked Loop with 50-Cycle Lock Time for High-Performance Low-Power Microprocessors","authors":"J. Lundberg, E. Nuckolls","doi":"10.1109/VLSIC.1994.586199","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586199","url":null,"abstract":"Introduction As microprocessor frequencies have increased, it has become necessary to de-skew internal and external clocks. It is also desirable to run internal docks faster than system clock rates. Clock generation via an analog PLL has previously performed this function(l), but as low-power applications for microprocessors proliferate, it has become necessary to use power management techniques. One such technique entails using a state wherein the on-chip clocks are quiescent, shutting down the microprocessor while statically maintaining machine states. Analog PLLs are not well suited to this since it is preferable that the PLL consume no power in this state. Furthermore, the frequency at which this state can be used is limited by how fast a PLL can stop and start (i.e., re-acquire phase lock). Slow PLL lock and stop times reduce the usage of this state and result in increased power consumption. This paper describes an alldigital PLL (ADPLL) with 50cycle lock time and lcycle shutdown to zero power. The ADPLL has process/temperature/voltage-independent gain for increased stability and is immune to inputclock jitter. At the ADPLL core is a digitallycontrolled oscillator (DCO) that runs at 4 times the reference frequency and has 16 bits of binarily-weighted control. The frequency and phase of the DCO are varied by arithmetically incrementing or decrementing the 16 control bits. The ADPLL achieves a skew-to-reference of less than 250ps and a peak-to-peak jitter under 125ps.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115091432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A 3-ghz 25-mw Cmos Phase-locked Loop 一个3ghz的25mw Cmos锁相环

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI: 10.1109/VLSIC.1994.586251

B. Razavi, Kwing F. Lee, R. Yan, R. Swartz

引用次数: 7