Proceedings of 1994 IEEE Symposium on VLSI Circuits最新文献

{"title":"A Ghz Mos Adaptive Pipeline Technique Using Variable Delay Circuits","authors":"M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, H. Yamada","doi":"10.1109/VLSIC.1994.586195","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586195","url":null,"abstract":"Introduction Two major obstacles are encountered in the production of practical GHz synchronous LSIs. The first is the excessive design margin that must be considered in trying to efficiently accommodate both deviations in circuit delay and clock skew: designers must consider not only the deviation in device parameters but also tlie variation in such operating-environmental factors as temperature, supply voltage, etc. The second major obstacle encountered is excessive power dissipation produced by high frequency LSIs as a result of tlie fact that all of their gates are operated at a single frequency determined on the basis of the critical path propagation delay time in just o n e of the pipeline stages, which has the niaximum critical path length. The delay time of the gates in each pipeline stage does not need to be tlie same. This waste of power needs to be eliminated. This paper presents an adaptive pipeline (APL) teclinique which automatically compensates for clock skew and which avoids the necessity of including as design factors either device parameter deviations or operating-environment variations. Further, by individually controlling gate delay for each pipeline stage, the APL technique is able to eliminate excessive power dissipation. In the APL technique, MOS current mode logic (MCML)[l] is used for the low noise and variable delay fundamental logic circuits. Tlie APL is here applied to a 0.4pni MOS 1.W lGHz G4bit double-stage pipeline adder.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116709677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Speed Programming and Program-Verify Methods Suitable for Low-Voltage Flash Memories","authors":"T. Tanaka, M. Kato, T. Adachi, K. Ogura, K. Kimura, H. Kume","doi":"10.1109/VLSIC.1994.586214","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586214","url":null,"abstract":"Three cffcctivc tcchniques arc proposed to achicve high-spccd programming and program-verify. A method of fixing the p-well bias for row sub-decoders allows the program-verify stage to follow the program stage wirhout an additional well-charging operation. By using an intemal program-end detection circuit, the completion of program mode is checked in one clock cycle, thus freeing the extemal processor from memory chips. The method of variable pulse width for programming reduces the total numser of verifications.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124630745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Median Peak Detecting Servo Analog Processor For Hard Disk Drives","authors":"K. Nagaraj, R. W. Walden, G. Offord, S. Lewis, J. A. Sabnis, R. Peruzzi, J. Barner, J. Plany, R. Mento, V. Rakshani, R. W. Hull","doi":"10.1109/VLSIC.1994.586231","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586231","url":null,"abstract":"The demodulation of embedded servo signals in hard disk drives is traditionally achieved either by peak detection [1,2] or by area integration [3]. Peak detection has the advantage of simplicity. However, simple peak detection lacks immunity against impairments in the signal. Area integration provides high immunity against wide-band additive noise in the signal but does not eliminate local media defects that occur due to clustering of particles [l]. Also, it is likely to be affected by errors in the demodulation itself (such as in pulse count). which in turn are caused by noise in the signal . To overcome these limitations, this paper describes an analog processor that selects the median of up to five successive peaks. The five-peak median reduces random noise power by a factor of 3. It also completely eliminates local defects with density of less than 3 out of 5 and is insensitive to errors in pulse count.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116468618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 13-Bit 10-Mhz Adc Background-Calibrated with Real-Time Oversampling Calibrator","authors":"T. Shu, B. Song, K. Bacrania","doi":"10.1109/VLSIC.1994.586166","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586166","url":null,"abstract":"A real-time digital-domain code-error calibration technique is developed and demonstrated in this fully-Merential5-volt 13-bit IO-= BiCMOS ADC. The calibration process does not interfere with the normal operation of the converter but improves its linearity in real time while the converter is working. The core of this technique is an oversampling sigma-delta ratio calibrator working synchronously with the converter in background.' 1. Introdiictiou Existing self-calibration techniques for data converters interrupt normal conversion cycle for calibration[ I]. Temperature variation, device parameter drift, etc., may cause the calibration data to become invalid unless the converter is periodically re-calibrated. Other analogdomain calibration techniques are limited by the analog signal accuracy and circuit noise[2]. A novel digital-domain, code-error background calibration technique is implemented in this experimental 13-bit 10-MHZ ADC. The calibration procedure is virtually trans arent to the normal converter operation, thus allowing tg e converter to operate continuously even while being calibrated. 2.Real-Time Digital Calibration Technique In a multi-stage type ADC, the linearity of the D-to-A converter @AC) in the first stage determines the overall transfer characteristics of the ADC. To calibrate the ADC it is necessary to correct the linearity error of the fist stage DAC. In this ADC, a resistor-string DAC is used in the first stage because it allows both the calibrator circuit and the ADC amplifier to tap different DAC outputs simultaneously without affecting each other, provided that the DAC outputs settle within the clock phase. The DAC output errors are digitized by the calibrator and later subtracted from the raw output codes with the code-error calibration technique[3], To measure the resistor DAC error, a ratio-measurement method has been used. A switched-capacitor subtracter is used to measure the mid-point voltage error of a given section of the resistor string. A simplified diagram is shown in Figxe 1. Assuming ideal conditions,C, = C2 = C,,","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116474811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Cmos Serial Link For 1 Gbaud Fully Duplexed Data Communication","authors":"Kyeongho Lee, Sungjoon Kim, Gijung Ahn, D. Jeong","doi":"10.1109/VLSIC.1994.586248","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586248","url":null,"abstract":"This paper describes a CMOS serial link allowing fully duplexed 1 Gbaud serial data communication. The bidirectional serial link comprises a transmitter, a bidirectional bridge, an impedance matching circuit, a 4 GHz data oversampler, and a digital PLL. Fully duplexed serial data communication is realized by the bidirectional bridge and process- independent clock and data recovery is accomplished by the digital PLL. A single channel serial link and a charge pump PLL are integrated in a chip. The chip is fabricated using 1.2 pm CMOS process technology. INTRODUCTION Today, data rates become higher on various data communication fields. A high speed bidirectional serial link is a robust, low-cost solution to the high data rate requirements of chip-to-chip, board-to-board, and system- to-system communication. The bidirectional serial link can be applied to processor-to-processor communications, graphics super computers, and I-IDTV, which require the highest data rate, and also to various I/O channels, LANs, satellite, fiber data communications. This paper proposes a CMOS bidirectional serial link allowing fully duplexed data transfers at 1 Gbaud.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121526954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Quick Boosting Charge Pump Circuit for High Density and Low Voltage Flash Memories","authors":"T. Tanzawa, Y. Tanaka, T. Tanaka, H. Nakamura, H. Oodaira, K. Sakui, M. Momodomi, S. Shiratake, H. Nakano, Y. Oowaki, S. Watanabe, K. Ohuchi, F. Masuoka","doi":"10.1109/VLSIC.1994.586217","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586217","url":null,"abstract":"I n t roduct ion T h e demand o f f a s t programmable f l a s h memorfes h a s been d r a s t i c a l l y i n c r e a s i n g f o r t h e replacem c n t of hard d isks by t h e semiconductor mcmories. A s i n g l e power s u p p l y EEPROM s u c h as a N A N D EEPRON [ l ] requi res t o g e n e r a t e a high vol tage on c h i p f o r i t s programming. The r i s i n g time f o r a high vol tage more s igni f icant ly occuples t h e t o t a l programming time, a c c o r d i n g as a h i g h e r d e n s i t y f lash memory increases Its i n t e r n a l c a p a c i t a n c e of t h e w i r i n g s a n d wel l s , and as t h e power s u p p l y moves t o w a r d t h e low v o l t a g e , T h i s p a p e r is devoted t o proposing a new c h a r g e pump c i r c u i t f o r a high dens i ty and low vol tage f l a s h memory which s h o u l d g c n e r a t e a high vol tage on chip v e r y fas t . Conccpt for a New Charge Pump Schcmc F o r t h e c o n v e n t i o n a l c h a r g e pump c i r c u i t . t h e number of s t a g e s connec ted in s e r i e s between t h e power s u p p l y and t h e o u t p u t o f t h e c h a r g e pump c i r c u i t is f i x e d , a s i l l u s t r a t e d In Flg.1 [ Z ] . This flxed number of s t a g e s i s so deslgned as to genera t e a c e r t a i n high v o l t a g e r e q u l r e d f o r programming. However , t h e c h a r g e t r a n s f e r e f f i c i e n c y I i 'P / ICC f o r t h e c h a r g e pump c i r c u i t i s g iven by l / ( n t l ) , where I C C and I P P a re t h e mean input and o u t p u t c u r r e n t s f o r t h e c h a r g e pump c i r c u i t . r e s p e c t i v e l y , and n is t h e number o f s t a g e s connected i n s e r i e s between t h e power supply and t h e o u t p u t of t h e c h a r g e pump c i r c u i t . As a r e s u l t , many s t a g e s connected In s e r i e s are so redundant Lhat t h e convent ional charge pump c i r c u i t no t o n l y c o n s u m e s t o o much power b u t a l s o l o w e r s t h e c h a r g e t r a n s f e r eff ic iency while t h e boosted v o l t age is not much higher than t h e power supply v o l t a g e i n t h e b e g i n n l n g o f o p e r a t i o n . Thereby , I t t a k e s longer time f o r t h e convent ional charge pump c l r c u l t t o g e n e r a t e a des i red v o l t a g e f o r programming when a h i g h e r d e n s i t y EEPROM i n c r e a s e s t h e l o a d c a p a c l t a n c e f o r t h e c h a r g e pump c i r c u l t and t h e power supply vol tage Is lowered. The proposed c h a r g e pump scheme c o n c e p t u a l l y presented in Flg.2 can change t h e number of s t a g e s and t h e capaci tance used f o r c h a r g e pumping. While t h c o u t p u t v o l t a g e I s n o t much h i g h e r t h a n t h e power supply v o l t a g e in t h e beginnlng, t h e number o f s t a g e s I s c o n t r o l l e d t o b e small a n d t h e capaci tance f o r c h a r g e pumping t o b e l a r g e so as t o increase t h e charge t r","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132788006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Atm in B-Isdn Communication Systems and Vlsi Realization","authors":"T. Koinuma, N. Miyaho","doi":"10.1109/VLSIC.1994.586155","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586155","url":null,"abstract":"The Asynchronous Transfer Mode (ATM) is considered to be a key technology for B-ISDN. This paper discusses VLSI trends and how VLSI's can be applied to realize ATM switching node systems for B-ISDN. Implementing a practical ATM node system will require the development of technologies such as high-throughput ATM switch LSI's with up to 10 Gb/s capacity and SDH termination technology based on optical fiber transmission. An ATM traffic-handling mechanism with Quality of Service (QoS) controls such as ATM layer performance monitoring, virtual channel handling, usage parameter control, and VP shaping requires several hundred thousand logic gates and several megabytes of high-speed static RAM; VLSI's must be introduced if such mechanisms are to be implemented. ATM node system architecture is based on design principles of a building-block-type structure and hierarchical multiplexing. The basic ATM call handling module, the AHM, is composed mainly of a line termination block and a self-routing switch block; we analyzed this module from the viewpoint of the amount of hardware it requires. Finally, future ATM node systems are discussed on the basis of 0.2-/spl mu/m VLSI development trends and hardware requirements such as the need for ultrahigh integration of logic gate with memory, multichip modules, and low power dissipation technology. >","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133479093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 256m Dram With Simplified Register Control For Low Power Self Refresh And Rapid Burn-in","authors":"Seung-Moon Yoo, Jin-Man Han, E. Haq, S. Yoon, Se-Jin Jeong, Byungchan Kim, Jung-Hwa Lee, Tae-Seong Jang, Hyung-Dong Kim, C. Park, D.I. Seo, C. S. Choi, Sooin Cho, C. Hwang","doi":"10.1109/VLSIC.1994.586228","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586228","url":null,"abstract":"A 256M DRAM featuring register controlled low power self refresh without toggling of internal addresses or predecoders, activation of all row lines in quick succession for rapid burn-in at wafer level and hierarchical I/O line scheme with flexible redundancy is developed. The 13.75 x 23.86 mm2 die size, 16M x16 DRAM with 3811s access time at 2.2V and 70 \"C has been fabricated using 0.25pm triple well CMOS technology.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117061396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 6-ns 4-mb Cmos Sram With Offset-voltage-insensitive Current Sense Amplifiers","authors":"K. Ishibashi, Koichi Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A. Fukami, N. Hashimoto, N. Ohki, A. Shimizu, T. Hashimoto, T. Nagano, T. Nishida","doi":"10.1109/VLSIC.1994.586239","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586239","url":null,"abstract":"A 4-Mb CMOS SRAM with 3.84 /spl mu/m/sup 2/ TFT load cells is fabricated using 0.25-/spl mu/m CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells. >","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"41 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120864484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Dynamic Current-offset Calibration (dcc) Sense Amplifier With Fish-bone Shaped Bitline (fbb) For High-density Srams","authors":"J. Takahashi, T. Wada, Y. Nishimura","doi":"10.1109/VLSIC.1994.586243","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586243","url":null,"abstract":"I n t r o d u c t i o n As the density of SRAM increases, a large number of block division has been required. As each block has its own pcriphcral circuits such as decoder and sense amplifier. the die size of the SRAM increases proportional to the number of the blocks. Reducing the number of local decoders is one answer to the problem. In this viewpoint, the SCPA architecture has becn proposed[l]. So the remaining problem is how to decrease the number of sense amplifiers. Since one sense amplifier is connected to a long bitline pair, two new problems appear. One is increased bitline capacitance, the other is a large bitline parasitic resistance. Both issues inevitably increase the sensing delay. Moreover, the offset caused by mismatch of devices also incrcases the sensing delay. In following sections, these problems are solved by using DCC and FBB. The DCC can improve the sensing delay by dynamically cancelling the current offset. Combining FBB and DCC, the problems of increased bitline rcsistance c m be solved. These effects of each scheme are explained by applying these technique to 16Mbit SRAM.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":" 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131978208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}