High-Speed Programming and Program-Verify Methods Suitable for Low-Voltage Flash Memories

Abstract

Three cffcctivc tcchniques arc proposed to achicve high-spccd programming and program-verify. A method of fixing the p-well bias for row sub-decoders allows the program-verify stage to follow the program stage wirhout an additional well-charging operation. By using an intemal program-end detection circuit, the completion of program mode is checked in one clock cycle, thus freeing the extemal processor from memory chips. The method of variable pulse width for programming reduces the total numser of verifications.