{"title":"用于1g波特全双工数据通信的Cmos串行链路","authors":"Kyeongho Lee, Sungjoon Kim, Gijung Ahn, D. Jeong","doi":"10.1109/VLSIC.1994.586248","DOIUrl":null,"url":null,"abstract":"This paper describes a CMOS serial link allowing fully duplexed 1 Gbaud serial data communication. The bidirectional serial link comprises a transmitter, a bidirectional bridge, an impedance matching circuit, a 4 GHz data oversampler, and a digital PLL. Fully duplexed serial data communication is realized by the bidirectional bridge and process- independent clock and data recovery is accomplished by the digital PLL. A single channel serial link and a charge pump PLL are integrated in a chip. The chip is fabricated using 1.2 pm CMOS process technology. INTRODUCTION Today, data rates become higher on various data communication fields. A high speed bidirectional serial link is a robust, low-cost solution to the high data rate requirements of chip-to-chip, board-to-board, and system- to-system communication. The bidirectional serial link can be applied to processor-to-processor communications, graphics super computers, and I-IDTV, which require the highest data rate, and also to various I/O channels, LANs, satellite, fiber data communications. This paper proposes a CMOS bidirectional serial link allowing fully duplexed data transfers at 1 Gbaud.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A Cmos Serial Link For 1 Gbaud Fully Duplexed Data Communication\",\"authors\":\"Kyeongho Lee, Sungjoon Kim, Gijung Ahn, D. Jeong\",\"doi\":\"10.1109/VLSIC.1994.586248\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a CMOS serial link allowing fully duplexed 1 Gbaud serial data communication. The bidirectional serial link comprises a transmitter, a bidirectional bridge, an impedance matching circuit, a 4 GHz data oversampler, and a digital PLL. Fully duplexed serial data communication is realized by the bidirectional bridge and process- independent clock and data recovery is accomplished by the digital PLL. A single channel serial link and a charge pump PLL are integrated in a chip. The chip is fabricated using 1.2 pm CMOS process technology. INTRODUCTION Today, data rates become higher on various data communication fields. A high speed bidirectional serial link is a robust, low-cost solution to the high data rate requirements of chip-to-chip, board-to-board, and system- to-system communication. The bidirectional serial link can be applied to processor-to-processor communications, graphics super computers, and I-IDTV, which require the highest data rate, and also to various I/O channels, LANs, satellite, fiber data communications. This paper proposes a CMOS bidirectional serial link allowing fully duplexed data transfers at 1 Gbaud.\",\"PeriodicalId\":350730,\"journal\":{\"name\":\"Proceedings of 1994 IEEE Symposium on VLSI Circuits\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1994.586248\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1994.586248","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Cmos Serial Link For 1 Gbaud Fully Duplexed Data Communication
This paper describes a CMOS serial link allowing fully duplexed 1 Gbaud serial data communication. The bidirectional serial link comprises a transmitter, a bidirectional bridge, an impedance matching circuit, a 4 GHz data oversampler, and a digital PLL. Fully duplexed serial data communication is realized by the bidirectional bridge and process- independent clock and data recovery is accomplished by the digital PLL. A single channel serial link and a charge pump PLL are integrated in a chip. The chip is fabricated using 1.2 pm CMOS process technology. INTRODUCTION Today, data rates become higher on various data communication fields. A high speed bidirectional serial link is a robust, low-cost solution to the high data rate requirements of chip-to-chip, board-to-board, and system- to-system communication. The bidirectional serial link can be applied to processor-to-processor communications, graphics super computers, and I-IDTV, which require the highest data rate, and also to various I/O channels, LANs, satellite, fiber data communications. This paper proposes a CMOS bidirectional serial link allowing fully duplexed data transfers at 1 Gbaud.