A 256m Dram With Simplified Register Control For Low Power Self Refresh And Rapid Burn-in

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI:10.1109/VLSIC.1994.586228

Seung-Moon Yoo, Jin-Man Han, E. Haq, S. Yoon, Se-Jin Jeong, Byungchan Kim, Jung-Hwa Lee, Tae-Seong Jang, Hyung-Dong Kim, C. Park, D.I. Seo, C. S. Choi, Sooin Cho, C. Hwang

引用次数: 12

Abstract

A 256M DRAM featuring register controlled low power self refresh without toggling of internal addresses or predecoders, activation of all row lines in quick succession for rapid burn-in at wafer level and hierarchical I/O line scheme with flexible redundancy is developed. The 13.75 x 23.86 mm2 die size, 16M x16 DRAM with 3811s access time at 2.2V and 70 "C has been fabricated using 0.25pm triple well CMOS technology.

查看原文本刊更多论文

一种具有简化寄存器控制的256m Dram，用于低功耗自刷新和快速老化

开发了一种256M DRAM，具有寄存器控制的低功耗自刷新，无需切换内部地址或前身，在晶圆级快速连续激活所有行线和具有灵活冗余的分层I/O线方案。该芯片尺寸为13.75 x 23.86 mm2, 16M x16 DRAM，在2.2V和70”C下具有3811s的访问时间，采用0.25pm三阱CMOS技术制造。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Proceedings of 1994 IEEE Symposium on VLSI Circuits

自引率

0.00%

发文量