回收能量逻辑的功耗测量

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI:10.1109/VLSIC.1994.586170

R. T. Hinman, F. Martin, Schlecht

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引用次数: 21

摘要

回收能量逻辑是一个低功耗逻辑拓扑供电和时钟由一个单一的交流电源电压。本文描述了电路的工作原理，并给出了测量结果，表明这种方法可以比传统的CMOS逻辑减少5到17倍的耗散。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Power Dissipation Measurements on Recovered Energy Logic

Recovered Energy Logic is a low power logic topology powered and clocked by a single ac supply volt- age. This paper describes the operation of the circuit and presents measurements showing that this approach can re- duce dissipation by a factor of 5 to 17 over conventional CMOS logic.

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Proceedings of 1994 IEEE Symposium on VLSI Circuits

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