A Digital Self Compensation Circuit for High Speed D/a Converters

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI:10.1109/VLSIC.1994.586160

Ook Kim, Jungwook Yang, Suk-ki Kim, Wonchan Kim

引用次数: 0

Abstract

This paper presents a digital self compensation method for video-rate D/A converters(DAC's). In this method, the compensation operation is isolated from the high speed operation of the current switch. Therefore, the errors of each element of the device can be corrected without interrupting the device operation. This method was implemented using standard 0.8 pnt CMOS technology. The measured Integral Nonlinearity of the IO-bit CMOS DAC decreased to 0.22LSB.

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用于高速数模转换器的数字自补偿电路

提出了一种视频速率D/ a转换器(DAC)的数字自补偿方法。在这种方法中，补偿操作与电流开关的高速操作相隔离。因此，可以在不中断设备运行的情况下，对设备各元件的误差进行校正。该方法采用标准的0.8 pnt CMOS技术实现。测量到的io位CMOS DAC的积分非线性降低到0.22LSB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of 1994 IEEE Symposium on VLSI Circuits

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