超低功耗dram的自动减压(avr)方案

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI:10.1109/VLSIC.1994.586229

M. Tsukude, M. Hirose, S. Tomishima, T. Tsuruda, T. Yamagata, K. Arimoto, K. Fujishima

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引用次数: 8

摘要

最近，手持设备对低功耗dram [l-3]的需求非常大。为了减少数据保留电流，dram应该具有1)长数据保留时间，2)刷新操作的低活动电流，以及3)低待机电流。本文介绍了高密度dram的新型电流节省技术。电压下变频器(Voltage-DownConvertor, VDC)和升压式感应接地(boost - senseground, BSG)方案的结合[4]实现了低有功电流b的降低

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Automatic Voltage-swing Reduction (avr) Scheme For Ultra Low Power Drams

LIntroduction Recently, low power DRAMs[l-3] are strongly needed for handheld machines. To reduce the data-retention current, the DRAMs should have 1)long data-retention time, 2)low active current for a refresh operation, and 3)low stand-by current. This paper describes new current saving techniques for the high-density DRAMs. The combination of the Voltage-DownConvertor (VDC) and Boosted-SenseGround (BSG) scheme[4] achieves the low active current b reducing

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Proceedings of 1994 IEEE Symposium on VLSI Circuits

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