3. Ogb/s, 272mw, 8:1 Multiplexer And 4.1gb/s, 388mw, 1:8 Demultiplexer

I . INTRODUCTION Optical transmission systems require multiplexer and demultiplexer chips as the major ingredients. There have been proposed and realized several architectures for multiplexers and demultiplexers. Such as the shift resister architecture, the interleaved architecture, the series gated architecture, and so on. In general, these previous architectures have aimed at high speed operation rather than low power dissipation. In multiplexers, the series gated architecture is effective in reducing power dissipation because the series gate can implement complex logic with fewer current sources. However, the architecture requires the 3-level for the series gate [l]. Thus it is difficult to lower the supply voltage for multiplexers. Furthermore, the architecture requires larger current to drive the 3-level series gate at high speed. On the other hand, the interleaved architecture is widely used in demultiplexers. In this architecture, conversion from serial to parallel data requires the lst, 2nd and 3rd stage flipflops [2]. This requires a large amount of hardware and therefore consumes much power. In this paper, 8:l multiplexer and 1% demultiplexer chips with low power dissipation are described. The multiplexer chip adopts the modified series gated architecture, while the demultiplexer chip adopts the modified interleaved architecture.