A 15- 150mhz, All-Digital Phase-Locked Loop with 50-Cycle Lock Time for High-Performance Low-Power Microprocessors

Introduction As microprocessor frequencies have increased, it has become necessary to de-skew internal and external clocks. It is also desirable to run internal docks faster than system clock rates. Clock generation via an analog PLL has previously performed this function(l), but as low-power applications for microprocessors proliferate, it has become necessary to use power management techniques. One such technique entails using a state wherein the on-chip clocks are quiescent, shutting down the microprocessor while statically maintaining machine states. Analog PLLs are not well suited to this since it is preferable that the PLL consume no power in this state. Furthermore, the frequency at which this state can be used is limited by how fast a PLL can stop and start (i.e., re-acquire phase lock). Slow PLL lock and stop times reduce the usage of this state and result in increased power consumption. This paper describes an alldigital PLL (ADPLL) with 50cycle lock time and lcycle shutdown to zero power. The ADPLL has process/temperature/voltage-independent gain for increased stability and is immune to inputclock jitter. At the ADPLL core is a digitallycontrolled oscillator (DCO) that runs at 4 times the reference frequency and has 16 bits of binarily-weighted control. The frequency and phase of the DCO are varied by arithmetically incrementing or decrementing the 16 control bits. The ADPLL achieves a skew-to-reference of less than 250ps and a peak-to-peak jitter under 125ps.