2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)最新文献

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Optimizing the Automated Detection of Atrial Fibrillation Episodes in Long-term Recording Instrumentation 优化长期记录仪器对房颤发作的自动检测
J. Wrobel, K. Horoba, A. Matonia, T. Kupka, N. Henzel, E. Sobotnicka
{"title":"Optimizing the Automated Detection of Atrial Fibrillation Episodes in Long-term Recording Instrumentation","authors":"J. Wrobel, K. Horoba, A. Matonia, T. Kupka, N. Henzel, E. Sobotnicka","doi":"10.23919/MIXDES.2018.8436835","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436835","url":null,"abstract":"The aim of this paper was to optimize and evaluate the performance of our method for automated recognition of AF episodes that has been based on classification of the selected features derived from the heart rate signal. The aggregation of the classified heart beats has been added to minimize the false positive cases being noted by the clinicians when the wristband AF recorder was applied for long-term monitoring. Proposed improvement of the automated method led to considerable increase of sensitivity and improvement of the positive predictive value. At the same time the detection algorithm remains easy to be implemented in the mobile instrumentation for long-term monitoring.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125187958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Topology-Driven Reliability Assessment of Integrated Circuits 集成电路拓扑驱动可靠性评估
Theodor Hillebrand, S. Paul, D. Peters-Drolshagen
{"title":"Topology-Driven Reliability Assessment of Integrated Circuits","authors":"Theodor Hillebrand, S. Paul, D. Peters-Drolshagen","doi":"10.23919/MIXDES.2018.8436642","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436642","url":null,"abstract":"In this paper a structured method is presented which optimizes integrated analogue circuits in terms of aging. The aging analyses of each sub block used in the method are presented. Subsequently, these blocks are used to improve the aging behavior of a two-stage Miller-OTA. Moreover, the whole capabilities of the method are evaluated constructing an aging-compensated amplifier from scratch being virtually immune to aging.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129792524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low Power, Low Chip Area, Programmable PID Controller Realized in the CMOS Technology 用CMOS技术实现的低功耗、低片面积、可编程PID控制器
T. Talaśka, R. Dlugosz
{"title":"Low Power, Low Chip Area, Programmable PID Controller Realized in the CMOS Technology","authors":"T. Talaśka, R. Dlugosz","doi":"10.23919/MIXDES.2018.8436634","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436634","url":null,"abstract":"The subject of the proposed paper is a novel, transistor level implementation (in the CMOS technology) of a programmable PID (proportional-integral-derivative) controller. In our work we focus on a discrete-time digital approach, as it facilities realization of a programmable structure which is more flexible. The novelty of the proposed solution relies on implementing the PID controller as a parallel and asynchronous structure, controlled by a simple 2-phases clock. Each of the P, I and D parts is realized as a separate channel with an own multi-bit multiplier, a summing circuit and a delay line (in the I and the D parts). The multiplier is realized as a binary tree circuit that works fully asynchronously. The implementation in the CMOS technology allows to obtain a small structure. For the input signals, and the coefficients of the PID controller encoded on 8-bits the total number of transistors does not exceed 13000. In the CMOS 180 nm technology the chip area approximately equals 0.15 mm2. Data rate is in this case even as high as 200–330 MHz, depending on the temperature and supply voltage, at very low power dissipation not exceeding 1 mW. Such a solution is suitable for various microsystems and embedded systems (used for example in automotive applications) in which small sizes and high data rate become very important features.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129849937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Footprints of RF CMOS Compact Modeling Technology From Wireless Communication To IoT Applications RF CMOS紧凑型建模技术从无线通信到物联网应用的足迹
S. Yoshitomi
{"title":"Footprints of RF CMOS Compact Modeling Technology From Wireless Communication To IoT Applications","authors":"S. Yoshitomi","doi":"10.23919/MIXDES.2018.8436911","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436911","url":null,"abstract":"This paper reviews the development of compact modeling technology of RF (Radio Frequency) MOSFETs. Author, who was involved in the research and development of RF compact models for many products, will look back the footprints of the important technical issues, which are still essential for the next generation of IoT and wireless applications, and gives outlook of the future related technology developments.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"90 42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129879516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comparison of Methods of Fuzzy Functions Minimization 模糊函数最小化方法的比较
A. Wielgus, Hubert Jatkowski
{"title":"Comparison of Methods of Fuzzy Functions Minimization","authors":"A. Wielgus, Hubert Jatkowski","doi":"10.23919/MIXDES.2018.8436589","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436589","url":null,"abstract":"This paper discusses the problem of two-level minimization of fuzzy logic functions which is an important step in multilevel synthesis. Selected algorithms of both exact and heuristic methods were implemented in order to compare their effectiveness and time complexity.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"23 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124501113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Twofold State Assignment for LUT-based Mealy FSMs 基于lut的粉状fsm的双状态分配
A. Barkalov, L. Titarenko, Kamil Mielcarek
{"title":"Twofold State Assignment for LUT-based Mealy FSMs","authors":"A. Barkalov, L. Titarenko, Kamil Mielcarek","doi":"10.23919/MIXDES.2018.8436895","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436895","url":null,"abstract":"A method is proposed for reducing hardware in LUT-based Mealy FSMs. The method is based on dividing the set of states by classes. Each state has two codes. This approach is used together with encoding of collections of outputs. An example of synthesis is given, as well as results of investigation.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131348811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
About Silicon Creations [advertisement] 关于Silicon Creations[广告]
{"title":"About Silicon Creations [advertisement]","authors":"","doi":"10.23919/mixdes.2018.8436749","DOIUrl":"https://doi.org/10.23919/mixdes.2018.8436749","url":null,"abstract":"","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116516100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ka Band Digitally Controlled Oscillator for FMCW Radar in 130 nm SiGe BiCMOS Technology 130 nm SiGe BiCMOS技术FMCW雷达Ka波段数字控制振荡器
Igor Butryn, Lukasz Wiechowski, Daniel Pietron, W. Pleskacz
{"title":"Ka Band Digitally Controlled Oscillator for FMCW Radar in 130 nm SiGe BiCMOS Technology","authors":"Igor Butryn, Lukasz Wiechowski, Daniel Pietron, W. Pleskacz","doi":"10.23919/MIXDES.2018.8436691","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436691","url":null,"abstract":"The paper presents a Digitally Controlled Oscillator (DCO) for a FMCW radar transceiver designed in IHP 130 nm BiCMOS SiGe technology. The circuit consist of a differential pair of heterojunction bipolar transistors (HBT), a capacitor bank and an inductor that are designed in HFSS Ansys software to improve the quality factor and decrease inductance. The presented oscillator provides a wide tuning range from 29 GHz to 40.5 GHz. The DCO is supplied from 1.8 V and dissipates 18 mW. The phase noise of the presented oscillator is equal to −91 dbc/Hz at 1 MHz from carrier frequency.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132555575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Embedded Systems 嵌入式系统
J. Peckol
{"title":"Embedded Systems","authors":"J. Peckol","doi":"10.23919/mixdes.2018.8436778","DOIUrl":"https://doi.org/10.23919/mixdes.2018.8436778","url":null,"abstract":"","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128814214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low Power Programmable Gain Integrated Front-End for Electromyogram Signal Sensing 一种用于肌电信号传感的低功耗可编程增益集成前端
Ehab A. Hamed, M. Atef, M. Abbas
{"title":"A Low Power Programmable Gain Integrated Front-End for Electromyogram Signal Sensing","authors":"Ehab A. Hamed, M. Atef, M. Abbas","doi":"10.23919/MIXDES.2018.8444557","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8444557","url":null,"abstract":"This paper presents the design and post layout simulation for electromyogram (EMG) front-end. The architecture is characterized by ultralow power consumption and gain reconfigurability. Three stages are designed to form the whole front-end. The first stage is extremely efficient single ended amplifier. The second stage is programable gain differential ended amplifier, to enhance the overall supply rejection ratio, common mode rejection ratio and the dynamic range. Finally, the third stage is a buffer stage to isolate the loading from the amplifier. The first two stages are designed with cascode MOSFETs to increase the midband gain. The full design was post-layout simulated using 130 nm CMOS technology. The results show that the design has 60.36 dB mid-band gain in range of 5.3 Hz to 1.72 kHz. Using a supply voltage of 1.1 V, the first two stages consume $pmb{1.06mu A}$. The input referred noise is $2.95mu mathrm{V}_{mathrm{rms}}$. The common mode and power supply rejection ratios are above 94.5 dB and 79.4 dB respectively.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115158999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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