2015 45th European Solid State Device Research Conference (ESSDERC)最新文献

{"title":"Theoretical analyses and modeling for nanoelectronics","authors":"G. Baccarani, E. Baravelli, E. Gnani, A. Gnudi, S. Reggiani","doi":"10.1109/ESSCIRC.2015.7313815","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313815","url":null,"abstract":"In this presentation we shortly discuss the evolution of Microelectronics into Nanoelectronics, according to the predictions of Moore's law, and some of the issues related with this evolution. Next, we address the requirements of device modeling related with an extreme device miniaturization, such as the band splitting into multiple subbands and quasi-ballistic transport. Physical models are summarized and a few simulation results of heterojunction TFETs are reported and discussed.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117101571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"E-mode AlGaN/GaN True-MOS, with high-k ZrO2 gate insulator","authors":"Mattia Capriotti, C. Fleury, O. Bethge, M. Rigato, S. Lancaster, D. Pogany, G. Strasser, Eldad Bahat Treidel, O. Hilt, F. Brunner, J. Würfl","doi":"10.1109/ESSDERC.2015.7324713","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324713","url":null,"abstract":"We report on fabrication of enhancement-mode True-MOS high electron mobility transistor (HEMT) with ZrO2 gate dielectric. The GaN cap and AlGaN layers in the gate area are completely recessed by dry etching up to the GaN channel layer. The increase in channel resistance subsequent to the recess is compensated by adopting sub-micrometer gates and the negative Vth shift is mitigated by using a high-k dielectric. The maximum output current of 0.45 A/mm for a 0.5 μm gate length shows that the above concept can be promising for switching applications.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115339885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High performance low A/R poly PN diode for 20nm node PCRAM cell switch","authors":"Young Ho Lee, Min Yong Lee, S. Baek, Jong Chul Lee, S. Chae, Hae-Chan Park, B. Lee, H. Kim","doi":"10.1109/ESSDERC.2015.7324728","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324728","url":null,"abstract":"High performance 20nm-node PCRAM cell switching was successfully realized with the remarkable Ion/Ioff characteristics employing low aspect ratio poly PN diode on metal. Nice Ion/Ioff ratio was obtained by modifying stack of diode adopted in-situ boron-doped poly SiGe and thermal optimization with spike RTA. Basically, boron has high solubility and activation rate in SiGe matrix. In-situ boron-doped poly SiGe on P+ region is expected to contribute to P+ Rc improvement. In this study, we found the unusual phenomenon that thermal process after pillar patterning does not influence dopant diffusion due mainly to isotropic thermal behavior. It means that RTA process before pillar patterning will be more effective for doping profile and activation engineering. By applying spike RTA and in-situ boron-doped poly SiGe on diode, P+ Rc was not degraded despite of skipping additional P+ADD IMP and P+ ADD RTA process. As a result, Ion and Ioff of 393uA/cell on the 2.8V and 92pA/cell on the -3.5V at 75°C were achieved at height of diode down to 1000Å.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122516699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Substrate noise isolation improvement by helium-3 ion irradiation technique in a triple-well CMOS process","authors":"Ning Li, Takeshi Inoue, T. Hirano, Jian Pang, Rui Wu, K. Okada, Hitoshi Sakane, A. Matsuzawa","doi":"10.1109/ESSDERC.2015.7324762","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324762","url":null,"abstract":"Helium-3 ion irradiation technique is proposed to improve silicon substrate noise isolation by creating a local semi-insulated region with a resistivity over 1kΩ-cm in low-resistive silicon substrate. Noise isolation is improved about 10dB at 2GHz after helium-3 ion irradiation in a 180-nm CMOS process. A 90% noise reduction has been achieved in the measurement results for test structures with guard rings. The noise isolation can be kept even after annealing at 200°C for 1 hour.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122387189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"EDMOS in ultrathin FDSOI: Effect of doping and layout of the drift region","authors":"Antoine Litty, S. Ortolland, D. Golanski, C. Dutto, S. Cristoloveanu","doi":"10.1109/ESSDERC.2015.7324731","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324731","url":null,"abstract":"We have already demonstrated the fabrication of a Dual-Ground Plane Extended Drain MOSFET with 28nm FDSOI technology. The detrimental consequences of ultrathin SOI film were mitigated by back-biasing the ground planes. In this paper, we explore for the first time the device optimization in 28 nm FDSOI node by doping the drift region. This solution requires additional and dedicated process steps but is free from back-biasing schemes. Following TCAD simulations, devices have been designed and fabricated with UTBB-FDSOI technology. DC measurements indicate that even in ultrathin film (7 nm) the doping of drift region is still a lever for achieving high-voltage (5V) MOSFET with promising performance.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114323259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Charge transfer speed analysis in pinned photodiode CMOS image sensors based on a pulsed storage-gate method","authors":"A. Pelamatti, V. Goiffon, A. Chabane, P. Magnan, C. Virmontois, O. Saint-Pé, M. B. Boisanger","doi":"10.1109/ESSDERC.2015.7324737","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324737","url":null,"abstract":"Driven by low noise applications, Pinned Photodiode (PPD) [1]-[3] CMOS Image Sensors (CIS) have recently become the main image sensors technology for both commercial and scientific applications. The PPD (schematized in Fig. 1a) consists in a buried photodiode, where the surface p+ implant, also referred to as pinning-implant, pins the surface at the substrate potential. This peculiar structure not only reduces the dark current (by isolating the PPD from the charges generated at the SiO2-Si interface), but also limits the maximum PPD potential, often referred to as pinning voltage [4], which corresponds to the full depletion condition. The presence of this “potential floor” enables true charge transfer from the PPD to the collection node (or to another buried channel), whereas in standard photodiodes only charge sharing between two capacitances is possible. The combination of these unique features has led in the last decade to the development of several PPD-based detectors for high speed applications, such as Time of Flight (ToF) applications [5]-[8], which require high speed readout of small packets of photo-charges. One of the main challenges involved in PPD-based high speed detectors is to reach the best temporal resolution by maximizing the charge transfer speed from the photo-generation site to the collection node. The transfer speed becomes even more critical for applications, such as space imaging applications, which require pixel pitches of several tens of μm (for example for optics-related constraints [9]). In the last decade much effort has been put into improving charge transfer speed by introducing a drift field in the PPD by modulating the PPD local potential [5], [7], [10]-[13]. However the existing solutions often involve design and/or geometrical constraints, can require the use of a custom technology, or might not be implementable for large pixel pitches (where only a small drift field can be induced, as the maximum potential variation which can be generated within the PPD is equal to the pinning voltage [14], which is often of the order of 1V, or lower, to ensure optimum charge transfer toward the floating diffusion (FD)).","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131900607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physical and electrical characterization of Mg-doped ZnO thin-film transistors","authors":"A. Shaw, T. J. Whittles, I. Mitrovic, J. Jin, J. S. Wrench, D. Hesp, V. Dhanak, P. Chalker, S. Hall","doi":"10.1109/ESSDERC.2015.7324751","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324751","url":null,"abstract":"The effect of Mg-doping on the valence and conduction bands of ZnO grown at 200 °C using atomic layer deposition has been investigated using a range of physical characterization techniques: X-ray photoemission spectroscopy, inverse photoemission spectroscopy and spectrocopic ellipsometry. The conduction band minimum is seen to increase with Mg content hence confirming the increased band gap. The physical characterization has been linked with modeling of thin-film transistor structures whereby a defect state based model has been employed to explain the transport mechanisms within the film.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123894875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"UTBB FDSOI technology flexibility for ultra low power internet-of-things applications","authors":"E. Beigné, J. Christmann, A. Valentian, O. Billoint, E. Amat, D. Morche","doi":"10.1109/ESSDERC.2015.7324739","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324739","url":null,"abstract":"In this paper, we propose to analyze FDSOI technology suitability for IoT applications and more specifically for autonomous Wireless Sensor Nodes. As IoT applications are extremely diversified there is a strong need for flexible solutions not only at design and architectural level but also at technological level. Moreover, as most of those systems are recovering their energy from the environment, they are challenged by low voltage supplies and low leakage functionalities. We detail in this paper some FDSOI 28nm characteristics and results demonstrating that this technology could be a perfect option for multidisciplinary IoT devices. Back Biasing capabilities and low voltage features are investigated demonstrating efficient high speed/low leakage flexibility.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129337173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of anomalous Random Telegraph Noise in Resistive Random Access Memory","authors":"F. Puglisi, L. Larcher, A. Padovani, P. Pavan","doi":"10.1109/ESSDERC.2015.7324766","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324766","url":null,"abstract":"In this paper we explore the features of complex anomalous Random Telegraph Noise (aRTN) in TiN/Ti/HfO2/TiN Resistive Random Access Memory (RRAM) devices. Careful systematic experiment, dedicated characterization techniques, and physics-based simulations are exploited to gain insights into the physics of this phenomenon. The RTN parameters (amplitude of the current fluctuations, capture and emission times) observed in the experiments are analyzed in a variety of operating conditions. Anomalous behaviors are examined and their statistical characteristics are analyzed. Physics-based simulations taking into account both the Coulomb interactions among different defects in the device and the possibility for defects to show metastable states are exploited to suggest a possible origin of the aRTN. Results highlight the importance of the electrostatic interactions among individual defects and the trapped charge.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"44 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122422659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"(Invited) silicene and phosphorene: Progress on the intriguing case of buckled atomic sheets","authors":"L. Tao, Weinan Zhu, Joon-Seok Kim, D. Akinwande","doi":"10.1109/ESSDERC.2015.7324740","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324740","url":null,"abstract":"Two-dimensional (2D) atomic sheets yield collective properties of mechanical flexibility, electrical control, optical transparency and high surface-to-volume ratio, which hold promise for advanced flexible nanoelectronics and sensors. This work explores two newly emerging 2D materials, silicene and phosphorene (the Si and P equivalent to graphene) and their air-stability and device study. The debut of silicene transistor confirms ambipolar transport behavior in atomically thin Si with greater gate modulation than graphene, indicating potential device reach beyond graphene. On the other hand, phosphorene exhibits high mobility and tunable direct bandgap even on plastic substrates, making it the most suitable contemporary 2D semiconductor that combines the merits of graphene and transitional metal dichalcogenides. This recent progress on silicene and phosphorene represent a renewed opportunity for future nanoscale and flexible devices.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128164299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}