{"title":"Unified system level model of adsorption/desorption process and sensing electronics for vapor trace detection of different molecules in the air","authors":"D. Strle, J. Trontelj","doi":"10.1109/ESSDERC.2015.7324747","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324747","url":null,"abstract":"In this work we describe a high level Matlab-Simulink model of a sensor system for vapor trace detection of different molecules in the air using array of differently functionalized capacitive sensors and extremely sensitive integrated electronic detection system. The model includes the adsorption/desorption process of differently modified sensors and high-level model of a low noise analog signal processing electronics. The proposed model makes possible to study the interactions, selectivity and sensitivity of the sensor system efficiently and forms the basis for the design of different modules of the sensor system, including pattern recognition algorithms. In this way, the design process has been shortened. A demonstrator measurements show promising detection limit of 3ppt of TNT in 1 Hz band which is close to the simulation results.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130150449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Scalability of planar FDSOI and FinFETs and What's in store for the future beyond that?","authors":"B. Doris, T. Hook","doi":"10.1109/ESSDERC.2015.7324738","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324738","url":null,"abstract":"Conventional planar transistors have been used throughout the semiconductor industry for the past several decades. Further miniaturization of conventional devices has been proven to be a significant challenge and thus the industry has transitioned to Planar Fully Depleted FETs and FinFETs. As we look out at technologies beyond 7nm node there are many barriers which appear to limit the scalability of FinFETs. Therefore it is important to consider the device architecture options that can serve as a replacement and enable further scaling to meet future technology requirements. This invited talk discusses the scalability of Fully Depleted FETs and FinFETs and also proposes options to enable continued scaling beyond 7nm node.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115253560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Stanojević, M. Karner, Martin Aichhorn, Ferdinand Mitterbauer, V. Eyert, C. Kernstock, H. Kosina
{"title":"Predictive physical simulation of III/V quantum-well MISFETs for logic applications","authors":"Z. Stanojević, M. Karner, Martin Aichhorn, Ferdinand Mitterbauer, V. Eyert, C. Kernstock, H. Kosina","doi":"10.1109/ESSDERC.2015.7324776","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324776","url":null,"abstract":"We present a simulation modeling chain for nano-scaled III/V quantum-well MISFETs. Our methods are based on physical rather than empirical modeling, which allows to obtain predictive simulation results with very few fitting parameters. We use a recent InGaAs-based technology from Intel [1] to validate our simulation results which show excellent agreement with measured capacitance and conductance curves. We further evaluate the properties of a 60 nm long InGaAs quantum-well transistor, finding a sub-threshold slope of 73.5 mV/dec and a DIBL of 103.8 mV/V. A fast numerical computational framework ensures high modeling flexibility; at the same time execution times are kept short making our approach an ideal replacement for empirical device modeling which is still pervasive in TCAD.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"34 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132149846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Ghidini, D. Merlini, Massimiliano Cannavo, M. Polignano, I. Mica, A. Galbiati, L. Zullino, Riccardo Turconi, S. Grasso, Maurizio Moroni, D. Codegoni
{"title":"H2 annealing for metallic contaminant reduction in BCD-SOI process: Benefits and drawbacks","authors":"G. Ghidini, D. Merlini, Massimiliano Cannavo, M. Polignano, I. Mica, A. Galbiati, L. Zullino, Riccardo Turconi, S. Grasso, Maurizio Moroni, D. Codegoni","doi":"10.1109/ESSDERC.2015.7324772","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324772","url":null,"abstract":"Contaminant reduction is a key issue for SOI substrate which cannot make use of back-side gettering. H2 annealing has been proven to be effective in Si reconstruction, influencing diffusion by breaking strained Si bonds and generating cavities for contaminant gettering. These properties could help in reducing contaminants in BCD-SOI process. Unfortunately, H2 annealing integration can be highly critical and the process optimization has to take into account 3-D morphology evolution and contaminant reduction efficiency. Aim of this work is to understand the physical mechanisms behind Si surface reconstruction and metallic contaminants reduction.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126042819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Ocker, S. Slesazeck, T. Mikolajick, S. Buschbeck, S. Günther, E. Yurchuk, R. Hoffmann, V. Beyer
{"title":"On the voltage scaling potential of SONOS non-volatile memory transistors","authors":"J. Ocker, S. Slesazeck, T. Mikolajick, S. Buschbeck, S. Günther, E. Yurchuk, R. Hoffmann, V. Beyer","doi":"10.1109/ESSDERC.2015.7324727","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324727","url":null,"abstract":"With technology scaling of embedded nonvolatile memories, voltage scaling below 12 V is a primary goal to maintain the area efficiency of the memory module. The SONOS technology shows promise as a technology for present and future low voltage memory cells. This paper examines the physics of scaled SONOS gate dielectrics in relation to reducing the operational voltage. In particular, we have examined the influence of tunnel oxide, nitride and top oxide thicknesses. The results are supported by electrical simulation of the SONOS gate dielectric. By properly scaling the dielectric films and utilizing electrical simulation we have determined a limit for scalability of the SONOS technology in terms of operation voltage.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"544 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133531531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abhishek A. Sharma, M. Skowronski, J. Bain, J. Weldon
{"title":"Novel CMOS-compatible a-Si based oscillator and threshold switch","authors":"Abhishek A. Sharma, M. Skowronski, J. Bain, J. Weldon","doi":"10.1109/ESSDERC.2015.7324721","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324721","url":null,"abstract":"Resistive switching devices and neuromorphic computing systems, while an attractive solution to minimize compute bottlenecks, suffer from sneak-path problem and area inefficient implementations respectively. This has prompted research in developing beyond-CMOS functional blocks that can serve as a compact single device circuit block (selector and oscillator respectively). In this work, we explore amorphous-Si based metal-semiconductor-metal (MSM) devices to serve this function. CMOS compatible Pt/a-Si/Cu stacks show negative differential resistance (NDR) that enables their operation as oscillatory elements and as non-linear threshold switches. As a first demonstration of oscillations in a-Si, we report frequency tunability from 5 kHz to 80 MHz by modulating the series ballast and by changing the source voltage. The devices show low-voltage (<; 1.2 V), low-power operation (<; 100 μW). As threshold switches, these devices show a resistance change of > 800 between ON and OFF states with a peak current density of > 0.3 MA/cm2 at 1 V. Through an analysis of the change in the snap-back time (persistence) and the peak ON-state current, we evaluate the change in the modes of operation of the device as a threshold switch and as an oscillator.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122710338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling of the conduction characteristics of voltage-driven bipolar RRAMs including turning point effects","authors":"J. Blasco, J. Suñé, E. Miranda","doi":"10.1109/ESSDERC.2015.7324709","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324709","url":null,"abstract":"A recursive model for the quasi-static current-voltage (I-V) characteristic of voltage-driven bipolar resistive RAM (RRAM) devices is reported. The model is based on the Krasnosel'skiĩ-Pokrovskiĩ hysteresis operator and accounts for the sequential creation and destruction of conductive channels spanning the dielectric film. It is shown in this work how the basic model formulation can be upgraded so as to include partial degradation and recovery effects occurring close to the SET and RESET transition edges.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116445804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Illarionov, M. Waltl, A. Smith, S. Vaziri, M. Östling, M. Lemme, T. Grasser
{"title":"Interplay between hot carrier and bias stress components in single-layer double-gated graphene field-effect transistors","authors":"Y. Illarionov, M. Waltl, A. Smith, S. Vaziri, M. Östling, M. Lemme, T. Grasser","doi":"10.1109/ESSDERC.2015.7324741","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324741","url":null,"abstract":"We examine the interplay between the degradations associated with the bias-temperature instability (BTI) and hot carrier degradation (HCD) in single-layer double-gated graphene field-effect transistors (GFETs). Depending on the polarity of the applied BTI stress, the HCD component acting in conjuction can either accelerate or compensate the degradation. The related phenomena are studied in detail at different temperatures. Our results show that the variations of the charged trap density and carrier mobility induced by both contributions are correlated. Moreover, the electron/hole mobility behaviour agrees with the previously reported attractive/repulsive scattering asymmetry.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129794329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A surface potential and current model for polarity-controllable silicon nanowire FETs","authors":"Jian Zhang, P. Gaillardon, G. Micheli","doi":"10.1109/ESSDERC.2015.7324710","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324710","url":null,"abstract":"Silicon nanowire FET (SiNWFET) with dynamic polarity control has been experimentally demonstrated and has shown large potential in circuit applications. To fully explore its circuit-level opportunities, a physics-based compact model of the polarity-controllable SiNWFET is required. Therefore, in this paper, we extend the solution for conventional SiNWFETs to polarity-controllable SiNWFETs. By solving the current continuity equation, the potential distribution and drain current is obtained. The model shows good aoreement with TCAD simulation. It can be used as the core to develop the complete compact model for polarity-controllable SiNWFETs.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126595825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Stadlober, E. Karner, Andreas Petritz, A. Fian, M. Irimia‐Vladu
{"title":"Nature as microelectronic fab: Bioelectronics: Materials, transistors and circuits","authors":"B. Stadlober, E. Karner, Andreas Petritz, A. Fian, M. Irimia‐Vladu","doi":"10.1109/ESSCIRC.2015.7313816","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313816","url":null,"abstract":"Over the last five years, a series of novel organic materials that either occur freely or are extracted from nature have been applied in transistors and simple electronic circuits (inverters) as biocompatible and biodegradable dielectrics and semiconductors. Although these materials have natural origin, are abundant on earth and in many respects were exploited by humanity since centuries or even millennia, they often do not deliver the expected outcome for high performance electronics. This situation motivated chemists to synthesize organic materials inspired by the natural ones (i.e. nature-inspired), with improved structures for high-performance organic electronics development. Here, we elaborate on the usage of the new class of naturally-occurring and nature-inspired organic materials employed in electronic circuits. Such novel structures impart high performance and high stability to integrated circuits, and hold the appealing features of biocompatibility and biodegradability. They carry a huge potential for achieving the sustainability goal in electronics industry, corroborated by resource efficiency and electronic waste reduction.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124893952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}