用于逻辑应用的III/V量子阱misfet的预测物理模拟

Z. Stanojević, M. Karner, Martin Aichhorn, Ferdinand Mitterbauer, V. Eyert, C. Kernstock, H. Kosina
{"title":"用于逻辑应用的III/V量子阱misfet的预测物理模拟","authors":"Z. Stanojević, M. Karner, Martin Aichhorn, Ferdinand Mitterbauer, V. Eyert, C. Kernstock, H. Kosina","doi":"10.1109/ESSDERC.2015.7324776","DOIUrl":null,"url":null,"abstract":"We present a simulation modeling chain for nano-scaled III/V quantum-well MISFETs. Our methods are based on physical rather than empirical modeling, which allows to obtain predictive simulation results with very few fitting parameters. We use a recent InGaAs-based technology from Intel [1] to validate our simulation results which show excellent agreement with measured capacitance and conductance curves. We further evaluate the properties of a 60 nm long InGaAs quantum-well transistor, finding a sub-threshold slope of 73.5 mV/dec and a DIBL of 103.8 mV/V. A fast numerical computational framework ensures high modeling flexibility; at the same time execution times are kept short making our approach an ideal replacement for empirical device modeling which is still pervasive in TCAD.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"34 5","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Predictive physical simulation of III/V quantum-well MISFETs for logic applications\",\"authors\":\"Z. Stanojević, M. Karner, Martin Aichhorn, Ferdinand Mitterbauer, V. Eyert, C. Kernstock, H. Kosina\",\"doi\":\"10.1109/ESSDERC.2015.7324776\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a simulation modeling chain for nano-scaled III/V quantum-well MISFETs. Our methods are based on physical rather than empirical modeling, which allows to obtain predictive simulation results with very few fitting parameters. We use a recent InGaAs-based technology from Intel [1] to validate our simulation results which show excellent agreement with measured capacitance and conductance curves. We further evaluate the properties of a 60 nm long InGaAs quantum-well transistor, finding a sub-threshold slope of 73.5 mV/dec and a DIBL of 103.8 mV/V. A fast numerical computational framework ensures high modeling flexibility; at the same time execution times are kept short making our approach an ideal replacement for empirical device modeling which is still pervasive in TCAD.\",\"PeriodicalId\":332857,\"journal\":{\"name\":\"2015 45th European Solid State Device Research Conference (ESSDERC)\",\"volume\":\"34 5\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 45th European Solid State Device Research Conference (ESSDERC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2015.7324776\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 45th European Solid State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2015.7324776","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

我们提出了一个纳米级III/V量子阱misfet的仿真建模链。我们的方法是基于物理而不是经验建模,这允许在很少的拟合参数下获得预测的模拟结果。我们使用英特尔最新的基于ingaas的技术[1]来验证我们的模拟结果,该结果与测量的电容和电导曲线非常吻合。我们进一步评估了60 nm长的InGaAs量子阱晶体管的性能,发现亚阈值斜率为73.5 mV/dec, DIBL为103.8 mV/V。快速的数值计算框架保证了高的建模灵活性;同时,执行时间很短,使我们的方法成为经验器件建模的理想替代品,经验器件建模在TCAD中仍然普遍存在。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Predictive physical simulation of III/V quantum-well MISFETs for logic applications
We present a simulation modeling chain for nano-scaled III/V quantum-well MISFETs. Our methods are based on physical rather than empirical modeling, which allows to obtain predictive simulation results with very few fitting parameters. We use a recent InGaAs-based technology from Intel [1] to validate our simulation results which show excellent agreement with measured capacitance and conductance curves. We further evaluate the properties of a 60 nm long InGaAs quantum-well transistor, finding a sub-threshold slope of 73.5 mV/dec and a DIBL of 103.8 mV/V. A fast numerical computational framework ensures high modeling flexibility; at the same time execution times are kept short making our approach an ideal replacement for empirical device modeling which is still pervasive in TCAD.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信