Charge transfer speed analysis in pinned photodiode CMOS image sensors based on a pulsed storage-gate method

A. Pelamatti, V. Goiffon, A. Chabane, P. Magnan, C. Virmontois, O. Saint-Pé, M. B. Boisanger
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引用次数: 8

Abstract

Driven by low noise applications, Pinned Photodiode (PPD) [1]-[3] CMOS Image Sensors (CIS) have recently become the main image sensors technology for both commercial and scientific applications. The PPD (schematized in Fig. 1a) consists in a buried photodiode, where the surface p+ implant, also referred to as pinning-implant, pins the surface at the substrate potential. This peculiar structure not only reduces the dark current (by isolating the PPD from the charges generated at the SiO2-Si interface), but also limits the maximum PPD potential, often referred to as pinning voltage [4], which corresponds to the full depletion condition. The presence of this “potential floor” enables true charge transfer from the PPD to the collection node (or to another buried channel), whereas in standard photodiodes only charge sharing between two capacitances is possible. The combination of these unique features has led in the last decade to the development of several PPD-based detectors for high speed applications, such as Time of Flight (ToF) applications [5]-[8], which require high speed readout of small packets of photo-charges. One of the main challenges involved in PPD-based high speed detectors is to reach the best temporal resolution by maximizing the charge transfer speed from the photo-generation site to the collection node. The transfer speed becomes even more critical for applications, such as space imaging applications, which require pixel pitches of several tens of μm (for example for optics-related constraints [9]). In the last decade much effort has been put into improving charge transfer speed by introducing a drift field in the PPD by modulating the PPD local potential [5], [7], [10]-[13]. However the existing solutions often involve design and/or geometrical constraints, can require the use of a custom technology, or might not be implementable for large pixel pitches (where only a small drift field can be induced, as the maximum potential variation which can be generated within the PPD is equal to the pinning voltage [14], which is often of the order of 1V, or lower, to ensure optimum charge transfer toward the floating diffusion (FD)).
基于脉冲存储门方法的固定型光电二极管CMOS图像传感器电荷转移速度分析
在低噪声应用的驱动下,钉住光电二极管(PPD) [1]-[3] CMOS图像传感器(CIS)最近成为商业和科学应用的主要图像传感器技术。PPD(如图1a所示)由埋置光电二极管组成,其中表面p+植入物(也称为钉入植入物)在衬底电位处钉住表面。这种特殊的结构不仅减少了暗电流(通过将PPD与SiO2-Si界面产生的电荷隔离),而且还限制了PPD的最大电位,通常称为钉住电压[4],这对应于完全耗尽的条件。这种“电位下限”的存在使电荷从PPD转移到收集节点(或另一个隐藏通道),而在标准光电二极管中,只有两个电容之间的电荷共享是可能的。这些独特功能的结合在过去十年中导致了几种基于ppd的高速应用探测器的发展,例如飞行时间(ToF)应用[5]-[8],这些应用需要高速读出小包光电电荷。基于ppd的高速探测器面临的主要挑战之一是通过最大限度地提高从光产生点到收集节点的电荷转移速度来达到最佳的时间分辨率。传输速度对于应用变得更加关键,例如空间成像应用,它需要几十μm的像素间距(例如光学相关的限制[9])。在过去的十年中,通过调制PPD局域电位[5],[7],[10]-[13],在PPD中引入漂移场来提高电荷转移速度已经做了大量的工作。然而,现有的解决方案通常涉及设计和/或几何限制,可能需要使用定制技术,或者可能无法实现大像素间距(其中只能诱导很小的漂移场,因为PPD内可以产生的最大电位变化等于固定电压[14],通常为1V或更低,以确保最佳电荷向浮动扩散(FD)转移)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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