NORCHIP 2012最新文献

{"title":"Lithography analysis of via-configurable transistor-array fabrics","authors":"V. D. Bem, A. Reis, R. Ribas","doi":"10.1109/NORCHP.2012.6403145","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403145","url":null,"abstract":"Regular fabrics are expected to mitigate manufacturing process variations, increasing the fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of lithography behaviour of transistor-array based regular fabrics. Four different approaches presented in the literature (VCC, INVA, VCLB and VCTA) have been evaluated through lithography simulations. The well-established concept of edge placement error (EPE) has been taken into account as lithography behavior metric.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128368539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"H.264/AVC motion estimation on FPGAs and GPUs: A comparative study","authors":"Iracu O. Santos, A. Lopes, B. M. Carvalho, E. Corrêa, M. Kreutz","doi":"10.1109/NORCHP.2012.6403101","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403101","url":null,"abstract":"Video compression has been receiving much deserved attention due to the widespread adoption of digital video technology, and the need of optimizing the storage and transmission of such media. In this paper, we are concerned with the optimization of one step of the H.264 compression standard, namely, the motion estimation, in which motion vectors coding the movement of macroblocks (or sub-macroblocks) between two frames are computed. Specifically, we present here a comparative study between two architectures that were used to implement the full search (FS) algorithm for single pixel precision according to the standard H.264/AVC. We are particularly concerned with the relation area × throughput of the two architectures. We report here on experiments performed on CIF, SD and full HD data, comparing the maximum throughput achieved and bandwidth required by the architectures.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126506364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Functional Built-In Self-Test for processor cores in SoC","authors":"R. Ubar, Viljar Indus, Oliver Kalmend, T. Evartson, E. Orasson","doi":"10.1109/NORCHP.2012.6403148","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403148","url":null,"abstract":"A methodology for organization of at-speed functional Built-In Self-Test in processors, based on real functional routines is presented. The proposed self-test includes on-chip test application and response collection by using the functionality of the processor under test. We use divide-and-conquer approach. At component level, tests are targeting faults in components. At processor level, the functionality of the processor is used to apply functional test patterns to each component at-speed. Differently from usual Built-in Self-Test schemes, the test patterns are not needed to store in the chip under test, they will be generated on-line by the resources of the system.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123973323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems","authors":"Haoyuan Ying, Kris Heid, T. Hollstein, K. Hofmann","doi":"10.1109/NORCHP.2012.6403131","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403131","url":null,"abstract":"The advantages of moving from 2-Dimensional Networks-on-Chip (NoCs) to 3-Dimensional NoCs for any application must be justified by the improvements in performance, power, latency and the overall system costs, especially the cost of Through-Silicon-Via (TSV). The trade-off between the number of TSVs and the 3D NoCs system performance becomes one of the most critical design issues. In this paper, we demonstrate a genetic algorithm (GA) based system optimization method, which can deliver the advanced system design setup through topology, routing algorithm, task mapping and tile placement. In comparison to the simulated annealing (SA) based design optimization method, our GA based method can achieve significant advantages. All the experiments have been done in GSNOC framework (written in SystemC-RTL), which can achieve the cycle accuracy and good flexibility.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"413 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124420328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SynZEN: A hybrid TTA/VLIW architecture with a distributed register file","authors":"Stefan Hauser, Nico Moser, B. Juurlink","doi":"10.1109/NORCHP.2012.6403142","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403142","url":null,"abstract":"The quest for higher performance within a certain power budget in the fields of embedded computing demands unconventional architectural approaches. To this end, in this paper we present synZEN (sZ): a (micro-)architecture that combines features of very long instruction word (VLIW) and transport triggered architectures (TTAs) to cover the needs of different applications. SynZEN features a distributed register file (RF) (i.e., each functional unit (FU) has its own RF) and a wide memory connection to exploit spatial data locality. FPGA synthesis results demonstrate that due to the distributed RF the sZ design can be implemented in less area (in terms of FPGA slices) than existing TTA and VLIW designs. Furthermore, using two micro-benchmarks we show that because of the wide memory connection, sZ outperforms both the TTA as well as the VLIW design.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125489803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Biochips: The integrated circuit of biology","authors":"J. Madsen","doi":"10.1109/NORCHP.2012.6403135","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403135","url":null,"abstract":"Microfluidic biochips integrate different biochemical analysis functionalities (e.g., dispensers, filters, mixers, separators, detectors) on-chip, miniaturizing the macroscopic chemical and biological processes often processed by lab-robots, to a sub-millimeter scale. These microsystems offer several advantages over the conventional biochemical analyzers, e.g., reduced sample and reagent volumes, speeded up biochemical reactions, ultra-sensitive detection and higher system throughput, with several assays being integrated on the same chip. Hence, microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the necessary functions for biochemical analysis. Microfluidic biochips have an immense potential in multiple application areas, such as clinical diagnostics, advanced sequencing, drug discovery, and environmental monitoring, to name a few. Consequently, over the last decade, biochips have received significant attention both in academia and industry. The International Technology Roadmap for Semiconductors 2011 has listed “Medical” as a “Market Driver” for the future, and many companies related to biochips have already emerged in recent years and have reported significant profits. There are several types of microfluidic biochips, each having advantages and limitations. In flow-based biochips the microfluidic channel circuitry on the chip is equipped with chip-integrated micro-valves that are used to manipulate the on-chip fluid flow. By combining several micro-valves, more complex units like mixers, micro-pumps, multiplexers etc. can be built up, with thousands of units being accommodated on a single chip. In droplet-based biochips, the liquid is manipulated as discrete droplets on an electrode array. Although biochips are becoming more complex everyday, Computer-Aided Design(CAD) tools for these chips are still in their infancy. Most CAD research has been focused on device-level physical modeling of components. Designers are using full-custom and bottom-up methodologies involving many manual steps to implement these chips. However, for both types of biochip, the synthesis process can be similar to that of the mapping process for multi-core microelectronic platforms, i.e., starting from a biochemical application and a given biochip architecture, determining the resource allocation, binding, scheduling and placement of the application operations. This talk will illustrate how techniques and methods from multi-core microelectronic platforms can be used to solve synthesis and optimization problems of biochips.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125514514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Testing of an off-chip NoC protocol using a BIST/Synthesizable Testbench approach","authors":"Saif Uddin, Johnny Öberg","doi":"10.1109/NORCHP.2012.6403128","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403128","url":null,"abstract":"To make systems infinitely scalable is the holy grail of chip design and crux that needs to be solved in order to invent a sustainable design methodology. Network-on-Chip (NoC) has been suggested as this solution as it replaces the traditional buses for on-chip interconnection purposes. However, to reach infinite scalability, off-chip extensions to the NoC protocols are needed in order to maintain scalability at an affordable cost of manufacturability. Going off-chip introduces more levels of complexity when it comes to testing, not only should the chip testing be speedy, the off-chip connections must also be testable in a fast manner, the fastest way being a set of BISTs testing the whole structure in parallel. In this paper, we present a BIST approach for testing an off-chip NoC protocol used in a 4×4 Network-on-Chip configuration. It has 16 processor-nodes implemented on four interconnected plesiochronous Altera Stratix-II FPGA boards, each board hosting a Quad-core NoC.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125565149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Energy efficient MIMO channel pre-processor using a low complexity on-line update scheme","authors":"Chenxin Zhang, H. Prabhu, L. Liu, O. Edfors, V. Öwall","doi":"10.1109/NORCHP.2012.6403103","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403103","url":null,"abstract":"This paper presents a low-complexity energy efficient channel pre-processing update scheme, targeting the emerging 3GPP long term evolution advanced (LTE-A) downlink. Upon channel matrix renewals, the number of explicit QR decompositions (QRD) and channel matrix inversions are reduced since only the upper triangular matrices R and R-1 are updated, based on an on-line update decision mechanism. The proposed channel pre-processing updater has been designed as a dedicated unit in a 65 nm CMOS technology, resulting in a core area of 0.242mm2 (equivalent gate count of 116K). Running at a 330MHz clock, each QRD or R-1 update consumes 4 or 2 times less energy compared to one exact state-of-the-art QRD in open literature.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126993368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Deembedding static nonlinearities of power amplifiers using least square error algorithm","authors":"Wei Wei, J. Mikkelsen, O. K. Jensen","doi":"10.1109/NORCHP.2012.6403125","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403125","url":null,"abstract":"This paper presents a deembedding method that introduces the least square error algorithm as a means to retrieve the static nonlinearities of the dispersive output of power amplifiers excited by wideband modulated signals. The characteristics of static nonlinearities are expressed as polynomials and the coefficients are extracted from measured data showing dispersive AM/AM and AM/PM distortion effects. The formulated static nonlinear function is suitable for both Wiener and Hammerstein PA model implementations. The proposed deembedding method is compared to previously proposed methods based on moving average algorithms or artificial neural networks, of comparable accuracy and the proposed method is found to simplify the deembedding procedure and in addition it leads to a simpler mathematical representation of the static nonlinearity.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128152515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA implementation of elementary generalized unitary rotation with CORDIC based architecture","authors":"P. Misans, U. Derums, Vents Kanders","doi":"10.1109/NORCHP.2012.6403102","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403102","url":null,"abstract":"This paper describes the first trial of implementation of generalized unitary Jacobi-like rotation (the device is called EGU-rotator, further referred to as rotator) purely based on the CORDIC algorithm into Altera's and Xilinx FPGAs. The basics and examples for factorization of the generalized rotation matrix (further, matrix) are given. The number of matrix shapes alternates in the range from 4 to 64 depending on the range of used angles (parameters). A unified algorithm for implementation of parametrical rotator is provided. Reconfigurable architecture of rotator is briefly described. The choice of architecture is determined by 3 addresses and they correspond to different shapes of the matrix. The comparison of device resources for different wordlengths, the number of CORDIC iterations and platforms is given. The complex rotator works approximately 3 times slower and consumes approximately 5 times more device resources than a single CORDIC rotator.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128917794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}