NORCHIP 2012最新文献_第6页

A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter 一种基于90纳米CMOS门环振荡器的二维游标时间-数字转换器

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403120

P. Lu, P. Andreani, A. Liscidini

引用次数: 4

An operational amplifier for high performance pipelined ADCs in 65nm CMOS 一种用于65nm CMOS中高性能流水线adc的运算放大器

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403114

Sima Payami, A. Ojani

引用次数: 7

Integration of TTA processor tools to Kactus2 IP-XACT design flow TTA处理器工具集成到Kactus2 IP-XACT设计流程

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403151

Lauri Matilainen, Sakari Lahti, Otto Esko, E. Salminen, T. Hämäläinen

引用次数: 0

PathAware: A contention-aware selection function for application-specific Network-On-Chips PathAware:针对特定应用的片上网络的竞争感知选择功能

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403149

Behrad Niazmand, M. Reshadi, A. Reza

{"title":"PathAware: A contention-aware selection function for application-specific Network-On-Chips","authors":"Behrad Niazmand, M. Reshadi, A. Reza","doi":"10.1109/NORCHP.2012.6403149","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403149","url":null,"abstract":"Network-on-Chip (NoC) has been introduced as a novel solution to overcome the constraints met in on-chip interconnection networks. Performance of NoCs is one of the important concerns of researchers and designers. One of the factors that can affect performance in on-chip networks is the occurrence of congestion when routing packets. In this paper we introduce an output selection function, named “PathAware”, which can be exploited with any adaptive routing algorithm. The main purpose is to address the situations in which more multiple output ports are chosen as candidates and to reduce latency and balance traffic load by selecting the appropriate output port leading to a minimal path. In order to avoid deadlock, we have exploited turn model adaptive routing algorithms. Simulation results demonstrate that when using “PathAware” selection function along with “West-First” and “Odd-Even” adaptive routing algorithms, it can outperform “Random”, “Buffer-Level” and “Neighboron-Path” selection functions in terms of latency and an improvement of 41% can be achieved (in best case), while imposing a negligible overhead on energy consumption.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127335032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Power efficient arrangement of oversampling sigma-delta DAC 过采样σ - δ数模转换器的节能设计

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403119

Nadeem Afzal, J. Wikner

引用次数: 2