Integration of TTA processor tools to Kactus2 IP-XACT design flow

Lauri Matilainen, Sakari Lahti, Otto Esko, E. Salminen, T. Hämäläinen
{"title":"Integration of TTA processor tools to Kactus2 IP-XACT design flow","authors":"Lauri Matilainen, Sakari Lahti, Otto Esko, E. Salminen, T. Hämäläinen","doi":"10.1109/NORCHP.2012.6403151","DOIUrl":null,"url":null,"abstract":"This paper presents a new freely available, open source design flow to accelerate the usage of application-specific processors in System-on-Chip designs. The proposed flow combines our Transport-Triggered Architecture (TTA) processor toolset and Kactus2 IP-XACT design environment. The IP-XACT standard and our Kactus2 tool make it easy to integrate and configure intellectual property (IP) components from multiple vendors whereas the configurable TTA provides a fast and efficient path from C-to-VHDL. We present 3 use cases for TTA: as a ready-made fixed accelerator, a general-purpose processor, and a tailored application-specific processor. Moreover, management of instance-specific data in IP-XACT is discussed. The combined design flow is presented in detail step-by-step, and the user time spent on each step is evaluated. Provided that C source codes and IP-XACT library are available, a non-HW oriented engineer can implement an FPGA based multiprocessor product in less than 5 hours.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"NORCHIP 2012","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHP.2012.6403151","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

This paper presents a new freely available, open source design flow to accelerate the usage of application-specific processors in System-on-Chip designs. The proposed flow combines our Transport-Triggered Architecture (TTA) processor toolset and Kactus2 IP-XACT design environment. The IP-XACT standard and our Kactus2 tool make it easy to integrate and configure intellectual property (IP) components from multiple vendors whereas the configurable TTA provides a fast and efficient path from C-to-VHDL. We present 3 use cases for TTA: as a ready-made fixed accelerator, a general-purpose processor, and a tailored application-specific processor. Moreover, management of instance-specific data in IP-XACT is discussed. The combined design flow is presented in detail step-by-step, and the user time spent on each step is evaluated. Provided that C source codes and IP-XACT library are available, a non-HW oriented engineer can implement an FPGA based multiprocessor product in less than 5 hours.
TTA处理器工具集成到Kactus2 IP-XACT设计流程
本文提出了一种新的免费可用的开源设计流程,以加速在片上系统设计中特定应用处理器的使用。提出的流程结合了我们的传输触发架构(TTA)处理器工具集和Kactus2 IP-XACT设计环境。IP- xact标准和我们的Kactus2工具可以轻松地集成和配置来自多个供应商的知识产权(IP)组件,而可配置的TTA提供了从c到vhdl的快速有效的路径。我们介绍了TTA的3个用例:作为现成的固定加速器、通用处理器和定制的特定应用处理器。此外,还讨论了IP-XACT中特定实例数据的管理。组合式设计流程一步一步详细介绍,并对用户在每一步上花费的时间进行了评估。如果有C源代码和IP-XACT库,非硬件工程师可以在不到5小时内实现基于FPGA的多处理器产品。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信