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An accurate fault location method based on configuration bitstream analysis 基于配置码流分析的故障精确定位方法
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403144
Zhou Jing, L. Zengrong, Chen Lei, Wang Shuo, Wen Zhiping, Chen Xun, Qi Chang
{"title":"An accurate fault location method based on configuration bitstream analysis","authors":"Zhou Jing, L. Zengrong, Chen Lei, Wang Shuo, Wen Zhiping, Chen Xun, Qi Chang","doi":"10.1109/NORCHP.2012.6403144","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403144","url":null,"abstract":"As SRAM-based FPGAs are increasingly being used; there are more and more researches on the SEU effects of FPGA. To emulate the effects of SEUs, a variety of fault injection techniques have been studied. As fault injection process is black box testing method, it helps little to SEU mechanism study. For further study of the SEU effects and the mitigation techniques, a novel accurate fault location method is studied in this paper. The Accurate Fault Location System (AFLS) based on this method is developed to locate faults, which are detected by the fault injection system, in the FPGA resources. The precise location of resource corresponding to the faults will be obtained by converting the configuration bit location into FPGA resource physical location. Using this system will help the study of SEU effects and the mitigation techniques, and then encourage the utilization of FPGAs for space-based applications.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116651022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low power Real Time Clock with high accuracy over large supply voltage range 低功耗实时时钟，在大电源电压范围内具有高精度
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403110
W. Gut, G. Hilber, D. Gruber, M. Kaufmann, Andreas Rauchenecker, T. Ostermann
{"title":"Low power Real Time Clock with high accuracy over large supply voltage range","authors":"W. Gut, G. Hilber, D. Gruber, M. Kaufmann, Andreas Rauchenecker, T. Ostermann","doi":"10.1109/NORCHP.2012.6403110","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403110","url":null,"abstract":"Low-power Real Time Clock (RTC) circuits are important parts in a variety of modern applications. In addition to the low power-consumption, the frequency stability of the oscillation circuit and the whole RTC is important. We propose a RTC circuit that shows a deviation between -95ppm and 3.27ppm of the oscillation frequency from the mean value. The Measurements have been carried out over a manufactured split lot (therefore including local and global corner variations) and over a supply voltage range from 1.6V up to 2.5V.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125837852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2.1 µW 76 dB SNDR DT-ΔΣ modulator for medical implant devices 用于医疗植入装置的2.1µW 76 dB SNDR DT-ΔΣ调制器
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403118
Ali Fazli Yeknami, A. Alvandpour
{"title":"A 2.1 µW 76 dB SNDR DT-ΔΣ modulator for medical implant devices","authors":"Ali Fazli Yeknami, A. Alvandpour","doi":"10.1109/NORCHP.2012.6403118","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403118","url":null,"abstract":"This paper presents a low-power 2nd-order discrete-time (DT) ΔΣ analog-to-digital converter (ADC) aimed for medical implant devices. The designed ΔΣ modulator with two active integrators (filters) employs power-efficient two-stage load-compensated OTAs with minimal load and rail-to-rail output swing, which provides higher power-efficiency than the two-stage Miller OTA. The modulator, implemented in a 65nm CMOS technology with a core area of 0.033 mm2, achieves 76-dB peak SNDR over a 500 Hz signal bandwidth, while consuming 2.1 μW from a 0.9 V supply voltage. Compared to previously reported modulators for such signal bandwidths, the achieved performance (FOM of 0.4 pJ/step) make the presented modulator one of the best among sub-1-V modulators in term of most commonly used figure of merit.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115046479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Behavioral modeling of nonlinear settling for multiple cascaded SC stages 多级联SC级非线性沉降行为建模
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403136
Jia Sun, T. Rahkonen, M. Neitola
{"title":"Behavioral modeling of nonlinear settling for multiple cascaded SC stages","authors":"Jia Sun, T. Rahkonen, M. Neitola","doi":"10.1109/NORCHP.2012.6403136","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403136","url":null,"abstract":"This paper presents an efficient method to model the settling transient response of cascaded switched capacitor stages. A sigma-delta modulator was designed using non-delaying integrators to study the settling error in cascaded stages. First, a settling error look-up table model was built by separate continuous-time simulations, and then this error model was used in a fast discrete-time Simulink model. The modeling methodology is described, and the results are compared against Verilog-A simulations.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122718786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Study and simulation of an example redundant FIR filter 一个冗余FIR滤波器的研究与仿真
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403121
Joakim Alvbrant, J. Wikner, J. wikner
{"title":"Study and simulation of an example redundant FIR filter","authors":"Joakim Alvbrant, J. Wikner, J. wikner","doi":"10.1109/NORCHP.2012.6403121","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403121","url":null,"abstract":"In this paper we present a study and simulation results of the structure and design of a redundant finite-impulse response (FIR) filter. The filter has been selected as an illustrative example for biologically-inspired circuits, but the structure can be generalized to cover other signal processing systems. In the presented study, we elaborate on signal processing properties of the filter if we apply a redundant architecture were different computing paths can be utilized. An option is to utilize different computing paths as inspired by biological architectures (BIAs). We present typical simulation results for a low-pass filter illustrating the trade-offs and costs associated with this architecture.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"1106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122920646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Variability-aware design of 55 nA current reference with 1.4% standard deviation and 290 nW power consumption 55na基准电流、1.4%标准差、290 nW功耗的可变性感知设计
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403109
F. Cucchi, S. Pascoli, G. Iannaccone
{"title":"Variability-aware design of 55 nA current reference with 1.4% standard deviation and 290 nW power consumption","authors":"F. Cucchi, S. Pascoli, G. Iannaccone","doi":"10.1109/NORCHP.2012.6403109","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403109","url":null,"abstract":"In this paper we present the design of a 0.18 μm CMOS current reference, which is very robust with respect to process variations (1.4% relative standard deviation measured over 23 samples) and with low power consumption of 290 nW. This result was obtained with devices that have low intrinsic sensitivity to process variability, such as diffusion resistors in a nanopower “classic” BJT-based bandgap topology. At the cost of a larger die area, we obtain a significant reduction of dispersion with respect to the best results available in the literature, with a low power consumption.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114212886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Electrical and human feedback 电和人的反馈
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403134
Hanspeter Schmid
{"title":"Electrical and human feedback","authors":"Hanspeter Schmid","doi":"10.1109/NORCHP.2012.6403134","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403134","url":null,"abstract":"In this paper, the difference between simple and complex research projects is explained and shown with two technical examples. One example is an analog pad driver for a microelectrode array in which as little feedback as possible was used in order to make it possible that one designer could design, layout and characterize it in two weeks, getting it first time right. Another example is a MEMS accelerometer that uses feedback around the full system to reach extraordinary performance: 19-bit SDNR over 300-Hz bandwidth with sufficient long-time offset stability for inertial navigation. Achieving this required special care in the project set-up. The main conclusions of this paper are philosophical rather than technical: There is a fundamental difference between simple and complex projects. Complex electrical feedback structures cause complex human feedback structures. Faced with complexity, designers should choose intuitively rather than rationally or analytically. And finally, the main determinant for the success of a complex project is the experience of the team members and the level of trust in the project team.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124511640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A measurement technique for the vibrating wire sensors 振动线传感器的测量技术
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403147
A. Simonetti
{"title":"A measurement technique for the vibrating wire sensors","authors":"A. Simonetti","doi":"10.1109/NORCHP.2012.6403147","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403147","url":null,"abstract":"Wireless sensor networks are becoming a reality in civil engineering. Various features as the low cost, feasibility of being supplied by energy harvesting techniques such as a low maintenance, make wireless sensor nodes a very attractive solution when compared to wired processing units. Vibrating wire strain gauges are a particular class of force transducers very simple to embed in reinforced concrete. Nevertheless, an optimal control of these sensors for the low-power applications, requires a dedicated measurement principle that differs from the proven techniques. In this work, we propose a strain measurement based on the RMS value of the harmonic response. Theoretical calculations and experimental results are also given to demonstrate its validity.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134511372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
KL-cut based digital circuit remapping 基于KL-cut的数字电路重映射
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403106
Lucas Machado, Mayler G. A. Martins, V. Callegaro, Renato P. Ribas, A. Reis
{"title":"KL-cut based digital circuit remapping","authors":"Lucas Machado, Mayler G. A. Martins, V. Callegaro, Renato P. Ribas, A. Reis","doi":"10.1109/NORCHP.2012.6403106","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403106","url":null,"abstract":"This paper introduces the concept of k and kl-cuts on top of digital mapped circuits in netlist representations. Such new approach is derived from the concept of k and kl-cuts on top of And-Inverter Graphs (AIGs), respecting the differences between these two representations. The main motivation to use kl-cuts on top of mapped circuits is to perform local optimization. An algorithm for enumerating kl-feasible cuts on top of mapped circuits is proposed. A remapping approach is also presented. Preliminary results show that this approach is able to reduce up to 19% in area and up to 24% in delay of mapped circuits from a subset of ISCAS'85 benchmarks.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115723196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A survey on mixed operating mode/self synchronization 混合工作模式/自同步研究综述
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403150
Dipak S. Marathe
{"title":"A survey on mixed operating mode/self synchronization","authors":"Dipak S. Marathe","doi":"10.1109/NORCHP.2012.6403150","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403150","url":null,"abstract":"Mixed Operating Mode (MOM) is a digital hardware system which utilizes the advantages of Synchronous and Asynchronous Sequential circuit. But, an Asynchronous sequential circuit suffers from essential hazard. Earlier there were two design philosophies: by the addition of delay elements to the state output, or by input gate modification. These approaches make the whole design slower. On the other hand, the latter approach is based on the assumption that the gate delays are always higher than any wire delay present in the network, but in VLSI circuits the above assumption may not be true and also GALS (Globally Asynchronous, Locally Synchronous)FPGA model has a major drawback of implementing AI(Asynchronous Interfaces) in FPGA devices. AI design style which is based on asynchronous controllers that provides communication between modules(called ports) subject to essential hazard. Using the concept of MOM results in not only saving the logic but also uses less power and making the whole design faster and more flexible. It also improves the throughput and reducing the latency, by satisfying the essential signal condition, this method is capable of providing robust ports, i.e. essential-hazard-free.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"44 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116934848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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