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An analog receiver front-end for capacitive body-coupled communication 用于电容体耦合通信的模拟接收器前端
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403137
P. Harikumar, Muhammad Irfan Kazim, J. Wikner
{"title":"An analog receiver front-end for capacitive body-coupled communication","authors":"P. Harikumar, Muhammad Irfan Kazim, J. Wikner","doi":"10.1109/NORCHP.2012.6403137","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403137","url":null,"abstract":"This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in today's system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/√Hz at 6.8 mW.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"304 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123205457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Optimal register allocation by augmented left-edge algorithm on arbitrary control-flow structures 基于增强左边缘算法的任意控制流结构的最优寄存器分配
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403107
Mark Ruvald Pedersen, J. Madsen
{"title":"Optimal register allocation by augmented left-edge algorithm on arbitrary control-flow structures","authors":"Mark Ruvald Pedersen, J. Madsen","doi":"10.1109/NORCHP.2012.6403107","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403107","url":null,"abstract":"A new algorithm for optimal register allocation in context of high-level synthesis is presented. In this paper we show how the greedy left-edge algorithm can be leveraged to obtain a globally optimal allocation, that is computed in polynomial time. By splitting variables at block boundaries, allows for allocation to be done using only quasi-local and local allocation - avoiding the complexity of true global allocation. As local allocation is much simpler than global allocation, this approach emphasizes efficiency and ease of implementation - at a cost of an increased number of register transfers compared to other allocators. Experiments show that runtime is linear for all practical purposes.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115256880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Memory-aware system scenario approach energy impact 内存感知系统场景方法能量影响
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403111
Iasonas Filippopoulos, F. Catthoor, P. G. Kjeldsberg, Elena Hammari, J. Huisken
{"title":"Memory-aware system scenario approach energy impact","authors":"Iasonas Filippopoulos, F. Catthoor, P. G. Kjeldsberg, Elena Hammari, J. Huisken","doi":"10.1109/NORCHP.2012.6403111","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403111","url":null,"abstract":"System scenario methodologies propose the use of different scenarios, e.g., different platform configurations, in order to exploit variations in computational and memory needs during the lifetime of an application. In this paper several extensions are proposed for a system scenario based methodology with a focus on improving memory organisation. The conventional methodology targets mostly execution time while this work aims at including memory costs into the exploration. The effectiveness of the proposed extensions is demonstrated and tested using two real applications, which are dynamic and suitable for execution on modern embedded systems. Reductions in memory energy consumption of 40 to 70% is shown.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"9 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116776789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A readout circuit for an uncooled IR camera with mismatch and self-heating compensation 一种具有失配和自热补偿的非制冷红外相机读出电路
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403138
Daniel Svard, C. Jansson, A. Alvandpour
{"title":"A readout circuit for an uncooled IR camera with mismatch and self-heating compensation","authors":"Daniel Svard, C. Jansson, A. Alvandpour","doi":"10.1109/NORCHP.2012.6403138","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403138","url":null,"abstract":"This paper presents a readout integrated circuit for an infrared focal plane array intended to be used in infrared network attached video cameras in surveillance applications. The focal plane array consists of 352×288 uncooled microbolometer detectors with a pitch of 25 μm. The circuit features mismatch correction and a non-linear ramped current pulse scheme for biasing of the detectors, in order to relax the dynamic range requirement of preamplifiers and ADC imposed by detector process variation and self-heating during readout. The integrated circuit is designed in a 0.35 μm standard CMOS process and a smaller 32×32 size test chip has been fabricated for verification. The test chip shows RMS input referred noise of 17 μV at 60 frames/second and dissipates 170 mW of power.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115178077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitter 具有0.8 ps抖动的2.5 GHz自补偿带宽跟踪锁相环
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403127
M. Yogesh, P. Sareen, M. Dietl, K. Dewan
{"title":"A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitter","authors":"M. Yogesh, P. Sareen, M. Dietl, K. Dewan","doi":"10.1109/NORCHP.2012.6403127","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403127","url":null,"abstract":"In a conventional charge-pump based PLL design, the loop parameters such as the bandwidth, jitter performance, charge-pump current, and pull-in range among others govern the architecture and implementation details of the PLL. Different loop parameter specification change with a change in the reference frequency and in most cases requires careful re-design of some of the PLL blocks. This paper describes the implementation of a semi-digital PLL for high bandwidth applications, which is self-biased, low-power and exhibits bandwidth tracking for all reference frequencies between 40 MHz and 2.5 GHz in 65nm CMOS technology.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116130823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A power scalable and high pulse swing UWB transmitter for wirelessly-powered RFID applications 功率可扩展和高脉冲摆动UWB发射机，用于无线供电RFID应用
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403099
J. Mao, Z. Zou, M. DavidSarmiento, F. Jonsson, Lirong Zheng
{"title":"A power scalable and high pulse swing UWB transmitter for wirelessly-powered RFID applications","authors":"J. Mao, Z. Zou, M. DavidSarmiento, F. Jonsson, Lirong Zheng","doi":"10.1109/NORCHP.2012.6403099","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403099","url":null,"abstract":"This paper presents a 3-5 GHz, high output amplitude, carrier-less based Ultra Wideband (UWB) transmitter for wirelessly powered RFID application. The UWB transmitter consists of a baseband pulse generator, a driver amplifier and an output on-chip filter. The baseband pulse generator and the driver amplifier are designed as zero DC power consuming circuit, which enables scalable power with the pulse rate. IC pad and bonding wire parasitics are considered to be absorbed as part of output filtering network, realizing package co-design. The simulation result shows that the proposed transmitter radiates 2.34 pJ/pulse energy with 1.63 V pulse amplitude. The total energy consumption under 1.8 V power supply is 18 pJ/pulse, corresponding to 13% energy efficiency.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116142663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A fault-aware low-energy spare core allocation in networks-on-chip 片上网络中故障感知的低能耗备用核分配
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403143
F. Khalili, H. Zarandi
{"title":"A fault-aware low-energy spare core allocation in networks-on-chip","authors":"F. Khalili, H. Zarandi","doi":"10.1109/NORCHP.2012.6403143","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403143","url":null,"abstract":"This paper proposes a fault-aware and low-energy technique to spare core allocation in mesh-based networks-on-chip. The proposed technique sets the place of spare cores among free non-failed processing cores, dynamically. Here, dynamically setting means that the places of spare cores are tuned for each application and not fixed in the platform statically. The analysis of a key point leads to introduce the proposed technique: Some tasks of each application can be known as critical, based on their vulnerabilities, the performance degradation, and the energy consumption overheads due to negative impacts of failure recovery. The proposed technique locates the spare cores near to the cores assigned to critical tasks. The results of 1,000,000 fault injection experiments show that the proposed technique leads communication energy reductions and performance improvement, compared to well-known related works.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123320905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A Novel on-chip ultra-low power temperature sensing scheme 一种新颖的片上超低功耗温度传感方案
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403108
S. Chouhan, K. Halonen
{"title":"A Novel on-chip ultra-low power temperature sensing scheme","authors":"S. Chouhan, K. Halonen","doi":"10.1109/NORCHP.2012.6403108","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403108","url":null,"abstract":"In this work, a CMOS based temperature sensor with Nano-watt power consumption is presented. The proposed scheme utilizes sensitivity of MOS towards temperature in subthreshold region. Sensor is composed of PMOS and NMOS group which subsequently generates voltages that are having positive and negative temperature coefficients respectively. It has been observed that on subtracting these voltages, resultant shows, highly linear dependence with temperature. The proposed scheme is implemented using AMS 0.35 μm standard CMOS technology, and it shows wide temperature sensing ranges from -40 °C to +140 °C with a power consumption of tens of Nano watts.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124904619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS 一个9位50MS/s异步SAR ADC在28nm CMOS
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403105
T. Cao, S. Aunet, T. Ytterdal
{"title":"A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS","authors":"T. Cao, S. Aunet, T. Ytterdal","doi":"10.1109/NORCHP.2012.6403105","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403105","url":null,"abstract":"In this paper, a design of an asynchronous differential SAR ADC is presented. The ADC uses a dynamic two-stage comparator with a current source to improve linearity, a digital SAR control logic, bootstrapped sampling switches with body effect reduction, and a charge redistribution differential DAC with a monotonic capacitor switching procedure where the metal-metal capacitor unit is only 1fF for high power efficiency. At a sample rate of 50MS/s and a supply voltage of 1V, the 9-bit SAR ADC achieves an ENOB of 8.84 bit and consumes 45 μW, resulting in an energy efficiency of 2.01 fJ/conversion-step. The circuits are designed and simulated with parasitic models using a commercially available 28nm bulk CMOS process.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117028358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Configurable RTL model for level-1 caches 一级缓存的可配置RTL模型
NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403112
Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander, P. Larsson-Edefors
{"title":"Configurable RTL model for level-1 caches","authors":"Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander, P. Larsson-Edefors","doi":"10.1109/NORCHP.2012.6403112","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403112","url":null,"abstract":"Level-1 (L1) cache memories are complex circuits that tightly integrate memory, logic, and state machines near the processor datapath. During the design of a processor-based system, many different cache configurations that vary in, for example, size, associativity, and replacement policies, need to be evaluated in order to maximize performance or power efficiency. Since the implementation of each cache memory is a time-consuming and error-prone process, a configurable and synthesizable model is very useful as it helps to generate a range of caches in a quick and reproducible manner. Comprising both a data and instruction cache, the RTL cache model that we present in this paper has a wide array of configurable parameters. Apart from different cache size parameters, the model also supports different replacement policies, associativities, and data write policies. The model is written in VHDL and fits different processors in ASICs and FPGAs. To show the usefulness of the model, we provide an example of cache configuration exploration.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128145363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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