A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS

Abstract

In this paper, a design of an asynchronous differential SAR ADC is presented. The ADC uses a dynamic two-stage comparator with a current source to improve linearity, a digital SAR control logic, bootstrapped sampling switches with body effect reduction, and a charge redistribution differential DAC with a monotonic capacitor switching procedure where the metal-metal capacitor unit is only 1fF for high power efficiency. At a sample rate of 50MS/s and a supply voltage of 1V, the 9-bit SAR ADC achieves an ENOB of 8.84 bit and consumes 45 μW, resulting in an energy efficiency of 2.01 fJ/conversion-step. The circuits are designed and simulated with parasitic models using a commercially available 28nm bulk CMOS process.