Variability-aware design of 55 nA current reference with 1.4% standard deviation and 290 nW power consumption

Abstract

In this paper we present the design of a 0.18 μm CMOS current reference, which is very robust with respect to process variations (1.4% relative standard deviation measured over 23 samples) and with low power consumption of 290 nW. This result was obtained with devices that have low intrinsic sensitivity to process variability, such as diffusion resistors in a nanopower “classic” BJT-based bandgap topology. At the cost of a larger die area, we obtain a significant reduction of dispersion with respect to the best results available in the literature, with a low power consumption.