Lucas Machado, Mayler G. A. Martins, V. Callegaro, Renato P. Ribas, A. Reis
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This paper introduces the concept of k and kl-cuts on top of digital mapped circuits in netlist representations. Such new approach is derived from the concept of k and kl-cuts on top of And-Inverter Graphs (AIGs), respecting the differences between these two representations. The main motivation to use kl-cuts on top of mapped circuits is to perform local optimization. An algorithm for enumerating kl-feasible cuts on top of mapped circuits is proposed. A remapping approach is also presented. Preliminary results show that this approach is able to reduce up to 19% in area and up to 24% in delay of mapped circuits from a subset of ISCAS'85 benchmarks.
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