An accurate fault location method based on configuration bitstream analysis

Abstract

As SRAM-based FPGAs are increasingly being used; there are more and more researches on the SEU effects of FPGA. To emulate the effects of SEUs, a variety of fault injection techniques have been studied. As fault injection process is black box testing method, it helps little to SEU mechanism study. For further study of the SEU effects and the mitigation techniques, a novel accurate fault location method is studied in this paper. The Accurate Fault Location System (AFLS) based on this method is developed to locate faults, which are detected by the fault injection system, in the FPGA resources. The precise location of resource corresponding to the faults will be obtained by converting the configuration bit location into FPGA resource physical location. Using this system will help the study of SEU effects and the mitigation techniques, and then encourage the utilization of FPGAs for space-based applications.