PathAware: A contention-aware selection function for application-specific Network-On-Chips

Abstract

Network-on-Chip (NoC) has been introduced as a novel solution to overcome the constraints met in on-chip interconnection networks. Performance of NoCs is one of the important concerns of researchers and designers. One of the factors that can affect performance in on-chip networks is the occurrence of congestion when routing packets. In this paper we introduce an output selection function, named “PathAware”, which can be exploited with any adaptive routing algorithm. The main purpose is to address the situations in which more multiple output ports are chosen as candidates and to reduce latency and balance traffic load by selecting the appropriate output port leading to a minimal path. In order to avoid deadlock, we have exploited turn model adaptive routing algorithms. Simulation results demonstrate that when using “PathAware” selection function along with “West-First” and “Odd-Even” adaptive routing algorithms, it can outperform “Random”, “Buffer-Level” and “Neighboron-Path” selection functions in terms of latency and an improvement of 41% can be achieved (in best case), while imposing a negligible overhead on energy consumption.